1 New TOT design for the LAV F.E. electronics M. Raggi, P. Valente G. Corradi, D. Tagnani LNF electronic service TDAQ Working Group 29/05/2009

2 Energy deposit in the LAV (Riccardo) Maximum energy deposit into LAV > 20 GeV The core of the distribution extends up to 10 GeV 80% of deposited energy is confined in a single block We want to measure with good efficiency energy deposit > 50MeV

3 Possible PMT working point PMT working point for MIP Gain ≈ (1-2)x10 6 ; E dep =80 MeV; N p.e. /MeV=0.3 Collected charge for MIP Q MIP ≈ 5 pC Signal wdt=20 ns V MIP = 2*Q MIP *50  /20ns = 25 mV PMT max expected signals No saturation observed in PMT for signals up to 25V V MAX <2*Q 20GeV *50  /20ns = 7 V max expected signal Variations within different blocks and fluctuations can produce signals of order ≈ 10 V

4 Immagini del segnale analogico

5 Read out electronics requirements Requirements Energy resolution ≈ 10%/√E Time resolution < 500 ps Max rate ≈ MHz x ch (will be lower in real life) Able to manage very large signals ≈10V Measure energy 20 MeV – 20 GeV xblock range Strategy Use Time Over Threshold to measure charge Use Pisa TDC card for the readout (HPTDC) Use 1 Tell1 x RING to reduce cost

6 Preliminary results of NINO tests with Pbgl cosmic ray signals

7 Nino ASIC chip ALICE TOF system –Charge range pC –Eight channels per ASIC. –Differential input –LVDS output –Output pulse width dependent on the charge of the input signal –Fast amplifier to minimize time jitter, i.e. first stage with a peaking time of 1 ns; –Discriminator threshold in the range 10–100 fC

8 Schematic of the NINO circuit Input Stage Threshold adjust circuit 4 stages of low gain High BW differential amplifiers. Pulse stretcher –Output signal width from MRPC varies 2-6 ns –Add 10 ns to out signal width to match HPTDC LVDS output driver to TDC

9 The LAV-NINO adapter card 8 ch lemo input (+4 V -4V dynamics) Each input is divided by 1, 1/10, 1/100 and sent to NINO 3x8 output channels into NINO board Single channel layout

10 Experimental setup LAV adapter + NINO VME READOUT Dual Range QDC +TDC(100ps)

11 NINO dynamic range test Experimental setup used to test NINO dynamic range: –Time wdt in the range ns have been explored –Amplitude range mV (20 ns) Use the NIM signal to: – Evaluate efficiency (scaler) –Measure signal width (Oscilloscope) LVDS to NIM Pulser FE+NINO Oscilloscope Scaler

12 Range tests results Using square waves we measure the time over threshold of corresponding NINO signals The NINO shows linear behavior up to 350 ns The intercept of the fit is due to the time stretcher circuit of NINO

13 Charge vs TOT test setup FE+NINO Amplifier x10 Discr. Bridge TDC ADC Discr. Scintillator

14 Typical NINO signal with Pbgl input

15 TDC hit map Trigger Signal The trigger on ch 31 shows cross level in TDC The signal shows cross talk between ch 6 and ch level (NINO ?) Signal

16 Signal width VS charge 1.6E -19 *3.5E 6 *0.35*70*10 = 140pC

17 TOT vs charge fit F=P1+P2  X+ P3  X 2 Limited charge range due to cosmic ray trigger Fit function can be improved

18 Charge resolution using TOT only AVERAGE RESOLUTION 8.5% TDC LSB 200 ps No correction applied TDC resolution 200 ps  1 = 6%  2 = 17.5% Noise contribution high due to 1/100 attenuation used.

19 Resolution VS charge

20 Conclusion and to do on NINO Max nominal charge in NINO correspond to half a MIP in LAV PMT Threshold range fc < gain too low The use of the Pbgl block in the trigger forced the charge to be too high in NINO (can use only 1/100 scale) Charge measurement with a precision <10% can be reached using TOT technique on LAV PMT signals To do list Build an external trigger based on scintillators or use the Pbgl test stand as a trigger system Set the PMT gain near the defined working point (1-2)x10 6 Enlarge the charge range changing the gain of the PMT

21 New TOT system for the LAV

22 Basic Ideas Build a low cost TOT system with larger dynamic wrt NINO asic –Use commercial devices (not a dedicated ASIC) –Clamp system able to maintain the TOT of original signal (needs very fast low capacitance diodes) –Amplify the signal a bit (x3) to allow correct reduce overdrive and to enlarge signal width (>15 ns) –Compare the amplified clamped signal with a low settable thr to start and stop the LVDS signal –Send an LVDS out to the TDC

23 Clamp stage: performance simulation Clamp input signals > 300 mV Requires very fast low-capacity HSMS-286C-TR1G schottky diodes HSMS-286C-TR1G diodes can suffer for too much power on it The power in excess is dissipated using properly dimensioned metal pads on the PCB The clamp maintain the trailing edge time of the original signal! No limit to maximum amplitude of signals to be measured using TOT! V In V Out

24 Single channel Layout Clamp stage Analog Inn Analog Out/2 Clamped Out LVDS Out Thr circuit x3 Amplifier Comparator

25 TOT resolution improvements TOT with low thr may suffer for noise on long signal tails Adding a pole (T 3 ) to signal tail allow a cleaner definition of trailing edge T 1 therefore better definition of the TOT Consequences on dead time to be understood thr Original signal Shaped signal Dead time 0 mV Part of the dead time (T 2 -T 1 ) is recovered by shortening the original signal Channel is no more considered dead [T 1 ;T 2 ] as it was for the original signal (risky business) T0T0 T1T1 T2T2 T4T4 T3T3 Total dead time (T 4 -T 0 ) increased by (T 4 -T 2 )

26 Board layout submitted 4 channels prototype board submitted to firm include: - 4 analog input channels - 4 direct analog out divided by clamped analog out - 4 independent thr adjust trimmers - LVDS out to CAEN TDC Foreseen studies: - Time stability of clamp trailing edge for large signals - Death time and max rate measurements - Time resolution - Energy resolution using TOT - Efficiency VS thr for MIP signals

27 Final readout scheme for VETO F.E. board For each ring Veto Switch 48x1Gb In out Veto Ring Veto Event Builder To Readout Pc FARM Whole LAV system 1MHz x 2x32Bit x10 ch ~ 640 Mbit 160 ch To L0 trigger 1xTELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch 5x32 ch In <4x1 Gb <1Gb/ring Eth Gbit 5 board 10x32 ch Out 256 ch 8x32 ch In 8 board 16x32 ch Out <4x1 Gb

28 Global L 0 layout for LAV TELL 1 Eth receiver 6xEth 1Gbit Eth Gbit L0 FPGA 6xEth 1Gbit Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit TELL 1 BOARD TDC 128ch Eth Gbit L0 FPGA TDC 128ch Eth Gbit Eth receiver under Rome2

29 # of electronics components ANTI-N # blocks (x ANTI) # F.E. card (x ANTI) # channels (x ANTI) # TDC (x ANTI) # TELL1 (x ANTI) ANTI (1-5) ANTI (6-7) ANTI (8-12) TOTAL (90)512048(60)12(15) Assumptions –1 scale for the whole dynamic range –32 ch per front end card –2 channels into TDC for each input (100% redundancy)

30 Naïve cost estimate ItemN TOT TOT Cost F.E. board (32 ch)81(90)<200 K€ * TDC (Pisa)48(60)12(15) K€ TDC cables?? ≈400 ???? 15K €** ?? TELL112(15)36(45) K€ Readout PC11 K€ 48X1Gbit switch11 K € Total cost≈260 K€ Does not include crates + power supply * Cost is an upper limit driven by the request of on board FPGA (real cost estimate needs final board design) ** Cable type to be defined cost is just a guess Final cost will be < 300K€

31 Conclusions The use of NINO in LAV electronic seem difficult –Dynamic range too small max 2 pC thr fC –3xN channels to allow 1000 range –Strange behavior for high charge signal (not understood) New TOT device: –Much higher dynamic range (commercial electronic) –High performance clamping stage included –No need for multiple scales Time scale for new prototype –Project submitted to firm on Monday this week –PCB delivery beginning of June –Test foreseen during July as soon as ANTI-A1 is finished