3/3/991 Minutes from the fall 98 DAQ meetings: TOF crate will always be running in the single event mode Silicon crate may pipeline several (4?) events in the internal buffers List of the VME modules required for implementation of the trigger control and event builder synchronization: Event Number Generator, ENG, located in one (master) of the VME crates. It generates Event#&Type. Interface to ENG, ING, located in all VME crates. It receives Event#&Type from the ENG. Trigger Registers, TR, located in the Trigger VME crate. It latches current trigger conditions. Enable Registers, ER, located in the Trigger VME crate. It enables/disables different trigger sources. Programmable Prescalers, 1/n, located in the Trigger VME crate. Using programmable logic devices like ispLSI from LATTICE it is possible to incorporate the functionality of the ENG, ING, TR, ER (and, possibly, 1/n) inside single module.ispLSI Let’s call it PCD (Programmable Control and Data ports). Each crate will have several PCD modules configured in different ways. For example in the Trigger crate it will be one PCD configured as ING, and several PCDs - as ER/TR. ispLSI The advantage of using ispLSI: In-field programming Definite delay 3-year experience CIn Control Input Port COut Control Input Port DIO Data In/Out Port dECL dTTL Functional diagram of the PCD Hardware for PHOBOS Trigger Control

3/3/992 1/n CC TR ER PP*PN(N) TR ER TR ER RP*RN(N) TR ER TR ER TOF LED Pulser TR ER TR ER Si Cal Pulser TR ER Pedestal Pulser Sync Event Calibration triggers Physics triggers CC LVL0 TR strobeTOF COM LVL0 at 300 nsec LVL0 BUSY GDG UDOS PP*PN(N) PRE (Pileup) Follow (TR) FO TR ER TR ER TR ER TR ER TR ER TR ER 1/n TR 1/n TR 1/n TR 1/n TR 1/n TR 1/n TR LVL0 VERTEX SUM ZCAL D 80 nsec 20 nsec LVL1 TR strobe Adjust for LVL1 timing ~1000 nsec LVL1 GDG D FAST CLEAR peaking Adjust for Si peaking time GDG 11 GDG 10 GDG 15 B1 LVL1 BUSY D Start LVL2 LVL2 L2 Event counter B2 Busy MDB Busy Event Manager ER = Enable Register (output), TR = Trigger Register (input), GDG = Gate and Delay Generator, FO = Fanout, 1/n = prescaler L1 Phobos Trigger Logic

3/3/993 Event#&Type code is 16bit word. Bits 0:11 represent sequential event number, bits 12:16 event type. TypeEvent Number All Phobos event types could be divided into 2 category: Normal Event when no special action required for any ROCs to handle the event. Special Event when special action required at least in one ROC. The typical event is the non zero-suppressed events in TOF. The additional information about enabled and actual trigger conditions could be obtained from the Trigger subevent. For example to identify that event was generated by TOF LED pulser, one need to check certain bit in the LVL0_TR word in the Trigger subevent. CIn Busy ROC0 Busy ROC1 Busy ROC2 TOF LED Sync Busy Event Gen DIO EvType 4bit Ev# 12bit L1 Event#&Type COut Strobe EOD 18 dTTL 16 dECL ispLSI Special Events PCD as the Event Number Generator

3/3/994 Event Types #code Description Special triggers TOF Pedestal (since Fastbus TDC and ADC are rather stable, the reasonable schedule for pedestal events will be 1 pedestal run with events per day) Silicon Pedestal (have to be defined) Silicon Calibration (have to be defined) Sync events (to synchronize Silicon and TOF in case of errors; generated in ENG) Reserved Special. Normal triggers Normal TOF LED (gain monitoring of TOF PMTs; trigger from LED electronics) Background events (empty buckets; triggered on beam crossing) Scaled down singles Reserved Normal triggers (fast multiplicity, flow triggers etc:) Event Types

3/3/995 Normal triggers. Normal triggers does not set Special Events field of CIn. The signal sequence is as follows: 1L1 arrives to ENG 2ENG sets Busy Event Gen in COut 3ENG increments Event# 4ENG transfers Event#&Type to all ROCs via DIO 5ENG waits falling edge of all Busy ROCs 6each ROC receives Event#&Type 7each ROC sets Busy ROC in CIn of ENG 8each ROC buffers event data 9each ROC removes Busy ROC in CIn of ENG 10ENG detects removal of all Busy ROCs 11ENG removes Busy Event Gen in CIn Special triggers. Let’s consider TOF LED Pulser. The hardware trigger is applied to the Calibration Trigger part of the trigger logic. The signal from the corresponding bit of the LVL0 TR goes to the TOF LED input of the control input port (CIn) ENG. The bit pattern of the Special Events field of CIn is transferred to the EventType field of data port DIO. Problem: Actually the ROC should turn off the zero-suppression before the event arrival. If we need to mix zero-suppressed events with non zero-suppressed in one run then TOF ROC should control the Pedestal Pulser like follows: 1TOF ROC generates Busy ROC 2TOF ROC turn off zero suppression 3TOF ROC removes Busy ROC 4TOF ROC generates Pedestal Pulser by writing to the local COut Signal Sequences

3/3/996 Sync event 1ENG sets Busy Event Gen 2ENG increments Event# and sets Type = Sync 3Continue as for Normal triggers from the step 4. … 10ENG detects removal of all Busy ROCs 11ENG repeats the steps 2:10 until all events in the Silicon pipeline are pushed out. Signal Sequences, Sync Event

3/3/997 CIn TR00 ER00TR strobe COut 16 dECL ispLSI ER15 ….. TR13 ….. VME CIn should latch TR data, the strobe propagation delay should be less than 20 ns. COut has level outputs (pulse outputs can be discussed). PCD as the Trigger/ Enable Register TR clear

3/3/998 dECL to TTL to dECL dTTL to TTL to dTTL MC10ELT25 MC10ELT24 SN74LBC978 HIGH ADR SEL A23-A8 A7-A1 AM5-AM0 AS LWORD IACK DS0-DS1 WRITE IACKIN DTACK BERR IACKOUT IRQn D00-D16 SYSCLK FIFO 64Kx18 DP0-DP15 STROBEs DIRs CPI0-CPI15 CPO0-CPO15 16MHz 64MHz C/ST FIFO SEL ispLSI INPUT CONTROL PORT 16 bit, 34pins connector OUTPUT CONTROL PORT 16 bit,34pins connector I/O DATA PORT 16 bit DATA+2 STROBEs 40pins connector VME P1 conn ector Block Diagram of the PCD

3/3/999 ispLSI DIO dTTL VME ispLSI DIO dTTL VME FIFO PCD-Transceiver in TOF/Trigger cratePCD-Receiver in Silicon crate 20MB/sec 64K*16 No need for Event Builder and CODA Simple, deterministic synchronization Data Transfer Using PCD (Suggestion)

3/3/9910 Schematic drawing is finished PCB design is ready feasibility analysis for implementation of 1/n Production of PCD boards ispLSI programming for ENG & ING ispLSI programming for TR&ER To Do: Current Status for 2/25/99

3/3/9911 ENG PPC INGTR&ER ING Silicon Trigger TOF ENG PPC INGTR&ER ING Silicon Trigger TOF RCVSNDRCV Minimal, with external Event Builder PPC: VME PowerPC processor ENG: Event number generator ING: Interface to ENG TR&ER: Trigger register and enable register RCV: receiving FIFO SND: sender Ethernet to EB Ethernet to Logger Maximal, with Event Builder inside one of the VME crates Configuration of the VME Crates