T1 hardware Detector Control System, OK several automates have been added, LV and HV sequences. FSM manages transition between Busy, ON and OFF states.

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Presentation transcript:

T1 hardware Detector Control System, OK several automates have been added, LV and HV sequences. FSM manages transition between Busy, ON and OFF states. Detector Safety System, OK Detector temperatures within expected range. Slow Control Loop, OK Main 40MHz LHC clock and Fast Command. DAQ system chain, OK added a firmware patch to the ORx mezzanine to increase the robustness of the system in the rare case the frame sent from the detector is corrupted. Trigger system, OK installed new fibers distribution patch panel. installed two new Trigger TOTFED boards with 3 ORxs each. deployed new Trigger TOTFED firmware FW OPTO Receiver FPGA, calculates the CSC hits multiplicity. FW Merger FPGA, calculates which sextant is fires based on majority voting (x out of 5 CSC planes) technique. Trigger chain under test, ready for next 90m  * run.

~6k wires VFAT CSC T1 ARM 1 Sbit 8 x ~6k wires VFAT CSC T1 ARM 1 Sbit 8 x2 1 x2x15 30 T1 TRG_TOTFED T1 TRG_TOTFED TOTEM TRG _TOTFED + LONEG Mezzanine VFAT 16 In 44 COUNTING ROOM CAVERN Trigger Bits 2 x 480 = 960 x2x15 x8 VFAT 16 In LV1 T1 trigger architecture Fibers Distribution Box

20/9/11 - Referees3 T1 trigger implementation fiber = 16 Trigger bits  Multiplicity encoded in 4 bits  + (thr) > (thr) T1_L1  (4bit*5 + 4bit*5) out of 64 4bit * 10 out of 64 + OptoRx 1 OptoRx 3 + OptoRx 2 SLSL SLSL S-Link 64 Connectors To LONEG Inputs + Trigger code Merger 40 out of 64 lines diff. lines

4 T1 trigger FW implementation (1) S  P #1 S  P #12 Fibers InFibers In 10+2 spares 16 Tbit Fiber Opto Receiver Tbit Sync 16 Tbit Mask En/Dis 16 Chamber Multiplicity Comp CLA Comp CLA 4 4 En/Dis OptoRx FPGA Programmable Scalers 20/9/11 - Referees Programmable Scalers

5 T1 trigger FW implementation (2) Sextant Majority comparator Output stage 4 * 10 CSC Multiplicity comparator Comp CLA Comp CLA Merger FPGA 4 * 10 Comp CLA OR1 OR2 OR3 >+ 1 bit x Sextant (6 bits) (Trigger code) To LONEG 20/9/11 - Referees 1 bit x CSC (30 bits) Thr Programmable Scalers

T1 trigger HW in IP5 Fibers Distribution Box T1 Trigger TOTFED System cabled In IP5 To LONEG