FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality of tester Status & outstanding issues

FED RAL: Greg Iles5 March What Needs To Be Tested ? Development Testing –Hardware Functionality test of front end & back end FPGA, Analogue performance, Power supplies, JTAG, S-Link, RAM, System configuration, modes etc.... –Software Development of API, and system under XDAQ Production Testing –Perhaps a subset of “development” tests Basic electronic connectivity/integrity (JTAG, factory visual/x-ray inspection) Communication interfaces (VME, TTC, S-Link...) Components (e.g. laser receivers) working ? Real world test that encompasses many features of the FED. Test it to the MAX !! System Testing –The whole Tracker system, including the FED, functions as expected. More of a software, rather than hardware test. 96 optical channels

FED RAL: Greg Iles5 March Requirements For 96 Channel Tester Requirements difficult to determine..... Requirements difficult to determine..... –All 96 channels independent ? Probably not, but should we have the capability ? –Temperature control over the laser transmitters ? Must not “fall out” of FED range (i.e. +/- 2 deg C) –Functionality required from a channel (e.g. number of different frames) ? Ideally full control –Time to verify a FED during production ? A few hours –Life expectancy and operating environment ? 10 years if used as test bench at CERN –Modify channel data without stopping system ? Yes, but may need to disable triggers

FED RAL: Greg Iles5 March U VME card Baseline Design Laser Driver 0Laser Driver 1Laser Driver 2Laser Driver 3Laser Driver 4Laser Driver 5Laser Driver 6Laser Driver 7 Switch (16 x 16) In 0-> Out 0 In 1-> Out 1, 2 etc..... Switch (16 x 16) In 0-> Out 6, 9 In 1-> Out 5 etc..... FPGA DA C Clk & Trigger Fibre Connectors AOH I2C Control Switch Control Temp I2C Control

FED RAL: Greg Iles5 March Functionality Of Tester –All 96 channels independent ? Present design has 3 independent channels per 24 channels and can be easily upgraded for full 96 independent channels if required. –Temperature control over the laser transmitters ? Laser diode DC output drift = 1MIP / deg C. We don’t want to fall out of the input range (13 MIPS) of the FED while testing Assume 9 MIPS for the APV => +/- 2 deg C Present design measures the temp to an accuracy of 0.2 deg C. Temperature should be stable to within a similar margin. –Functionality required from a channel Store over 200 APV 12bit frames in dual port memory. Each APV has 1000 deep arbitrary sequence of frames. Channels can be delayed by clk, clk/3 and sub ns New frames uploaded without stopping “ticks”, but may need to stop triggers. –Trigger master or slave ? System acts as a slave (i.e. responds to triggers by generating frame) Can simulate trigger errors

FED RAL: Greg Iles5 March Status & Outstanding Issues Status –Front end schematic finished and in layout so the temperature behaviour can be assessed. Control via I2C allows easy testing –VHDL code written to verify that internal dual port memory will run at the necessary 120MHz. Seems OK at the moment Fits within XC2V500 Outstanding Issues –Limited spare IO on FPGA ? Larger ~450 pin FPGA Second FPGA ? –Do we want a TTC connector ? Need to plan for it –Anything else we might want ?

FED RAL: Greg Iles5 March Conclusions Conclusions... –Integrated solution. Generates APV analogue signal on board. Controls laser driver temperature via I2C. Controls analogue-opto hybrid via I2C. Clock and Trigger management distribution. –Upgrade path to 96 independent channels if required. –Reuses as much of existing designs as possible. Analogue front end of current single channel system. VME interface of APVE.

FED RAL: Greg Iles5 March 20038

FED RAL: Greg Iles5 March 20039