Mar. 12, 2009Wu, Jinyuan Fermilab1 Several Topics on TDC and the Wave Union TDC implemented in FPGA Wu, Jinyuan Fermilab LBNL, Mar. 2009

Mar. 12, 2009Wu, Jinyuan Fermilab2 Features of FPGA TDC Fast Turn Around: –1– min recompile time. Sufficiently Good Resolution: –D–Delay line based: as good as 10ps. Low Cost at Small Volume: –8–8ch are implemented in EP2C8T144C6 ($31.68). Flexibility of DAQ Integration: –T–Trigger, event packing, serialization etc. can be integrated in the same device.

Mar. 12, 2009Wu, Jinyuan Fermilab3 FPGA TDC: a Single Chip Solution TDC FPGA TDC FPGA TDC DAQ V TH PMT In PMT In The differential input of the FPGA is a comparator. It is possible to directly interface analog signals. VBVB

Mar. 12, 2009Wu, Jinyuan Fermilab4 Actual Board and Circuit TDC FPGA TDC DAQ

Mar. 12, 2009Wu, Jinyuan Fermilab5 TDC Using FPGA Logic Chain Delay In Cyclone II chips, carry chain in a (ripple) adder is used as the delay line. The registers recodes each bit of the adder result. A priority encoder follows the array. IN CLK

Mar. 12, 2009Wu, Jinyuan Fermilab6 Two Major Issues Due To Differential Non-Linearity 1.Widths of bins are different and varies with supply voltage and temperature. 2.Some bins are ultra-wide due to LAB boundary crossing

Mar. 12, 2009Wu, Jinyuan Fermilab7 Digital Calibration Using Twice-Recoding Method IN CLK Use longer delay line. Some signals may be registered twice at two consecutive clock edges. N 2 -N 1 =(1/f)/  t The two measurements can be used: –to calibrate the delay. –to reduce digitization errors.

Mar. 12, 2009Wu, Jinyuan Fermilab8 Digital Calibration Result Power supply voltage changes from 2.5 V to 1.8 V, (about the same as 100 o C to 0 o C). Delay speed changes by 30%. The difference of the two TDC numbers reflects delay speed. 2 nd TDC 1 st TDC Corrected Time Warning: This is only an average bin width calibration, not bin-by-bin.

Mar. 12, 2009Wu, Jinyuan Fermilab9 Histogram Based Auto Calibration DNL Histogram In (bin) LUT  Out (ps) 16K Events It provides a bin-by-bin calibration at certain temperature. It is a turn-key solution (bin in, ps out) It is semi-continuous (auto update LUT every 16K events)

Mar. 12, 2009Wu, Jinyuan Fermilab10 Good, However Auto calibration solved some problems However, it won’t eliminate the ultra-wide bins 

Mar. 12, 2009Wu, Jinyuan Fermilab11 Cell Delay-Based TDC + Wave Union Launcher Wave Union Launcher In CLK The wave union launcher creates multiple logic transitions after receiving a input logic step. The wave union launchers can be classified into two types: Finite Step Response (FSR) Infinite Step Response (ISR) This is similar as filter or other linear system classifications: Finite Impulse Response (FIR) Infinite Impulse Response (IIR)

Mar. 12, 2009Wu, Jinyuan Fermilab12 Wave Union Launcher A (FSR Type) In CLK 1: Unleash0: Hold Wave Union Launcher A

Mar. 12, 2009Wu, Jinyuan Fermilab13 Wave Union Launcher A: Two Measurements in One Array 1: Unleash

Mar. 12, 2009Wu, Jinyuan Fermilab14 Sub-dividing Ultra-wide Bins Improving Sensitivity 1: Unleash Plain TDC: –Max. bin width: 160 ps. –Average bin width: 60 ps. Wave Union TDC A: –Max. bin width: 65 ps. –Average bin width: 30 ps.

Mar. 12, 2009Wu, Jinyuan Fermilab15 Auto Calibration for Wave Union TDC A DNL Histogram In (bin) LUT  Out (ps) 0 It is not possible and not necessary to control the relative timing of two edges precisely. Use TN1+TN2 as input for calibration.

Mar. 12, 2009Wu, Jinyuan Fermilab16 Measurement Result for Wave Union TDC A Histogram Raw TDC + LUT 53 MHz Separate Crystal -- Wave Union Histogram Plain TDC: –delta t RMS width: 40 ps. –25 ps single hit. Wave Union TDC A: –delta t RMS width: 25 ps. –17 ps single hit.

Mar. 12, 2009Wu, Jinyuan Fermilab17 More Measurements Two measurements are better than one. Let’s try 16 measurements?

Mar. 12, 2009Wu, Jinyuan Fermilab18 Wave Union Launcher B (ISR Type) Wave Union Launcher B In CLK 1: Oscillate0: Hold

Mar. 12, 2009Wu, Jinyuan Fermilab19 Wave Union Launcher B: Screen Dump 1 Hit MHz VCCINT =1.20V VCCINT =1.18V

Mar. 12, 2009Wu, Jinyuan Fermilab20 Delay Correction Delay Correction Process: Raw hits TN(m) in bins are first calibrated into TM(m) in picoseconds. Jumps are compensated for in FPGA so that TM(m) become T0(m) which have a same value for each hit. Take average of T0(m) to get better resolution. The raw data contains: U-Type Jumps: [48-63]  [16-31] V-Type Jumps: other small jumps. W-Type Jumps: [16-31]  [48-63] The processes are all done in FPGA.

Mar. 12, 2009Wu, Jinyuan Fermilab21 The Test Module Two NIM inputs FPGA with 8ch TDC Data Output via Ethernet BNC Adapter to add 150ps step.

Mar. 12, 2009Wu, Jinyuan Fermilab22 Test Result On Board Signal RMS 9ps - Wave Union TDC B + + Two independent crystals for: Driving TDC Creating test hits

Mar. 12, 2009Wu, Jinyuan Fermilab23 Test Result NIM Inputs 0 12 RMS 10ps LeCroy 429A NIM Fan-out NIM/ LVDS NIM/ LVDS - 140ps Wave Union TDC B + + BNC adapters to add 140ps step.

Mar. 12, 2009Wu, Jinyuan Fermilab24 Performance Device: EP2C8T144C6, Price: $28 (April 2008), Operating Frequency: 400MHz, Total Logic Elements: 8256 Max bin width Av bin width DT RMS error Dead Time Delay Chain Length Logic Element Usage Un-calibrated TDC 165ps60ps58ps2.5ns (21%) Plain TDC165ps60ps40ps2.5ns Wave Union TDC A 65ps30ps25ps5ns Wave Union TDC B 10ps45ns6581 (83%) 8CH

Mar. 12, 2009Wu, Jinyuan Fermilab25 Some Deleted Slides Resource usage in TDC depends on the measurement resolution strongly. To improve resolution by a factor of 2 may increase resource usage by a factor of 4 with the same base design.

Mar. 12, 2009Wu, Jinyuan Fermilab26 Test Result (1) 0 12 RMS 20ps LeCroy 429A NIM Fan-out NIM/ LVDS NIM/ LVDS - 150ps Wave Union TDC B BNC adapters to add 150ps step.

Mar. 12, 2009Wu, Jinyuan Fermilab27 Test Result (2) 0 12 RMS 14ps LeCroy 429A NIM Fan-out NIM/ LVDS NIM/ LVDS - 150ps Wave Union TDC B + +

Mar. 12, 2009Wu, Jinyuan Fermilab28 Test Result (3) 0 12 RMS 10ps LeCroy 429A NIM Fan-out NIM/ LVDS NIM/ LVDS - 140ps Wave Union TDC B + +

Mar. 12, 2009Wu, Jinyuan Fermilab29 Slower But Cheaper Multi-sampling TDC uses significantly less resources. Typical resolution is 500ps-1ns (LSB) or ps (RMS). This scheme is suitable for drift chamber applications.

Mar. 12, 2009Wu, Jinyuan Fermilab30 Multi-Sampling TDC FPGA c0 c90 c180 c270 c0 Multiple Sampling Clock Domain Changing Trans. Detection & Encode Q0 Q1 Q2 Q3 QF QE QD c90 Coarse Time Counter DV T0 T1 TS Ultra low-cost: 48 channels in $18.27 EP2C5Q208C7. Sampling rate: 360 MHz x4 phases = 1.44 GHz. LSB = 0.69 ns. 4Ch Logic elements with non-critical timing are freely placed by the fitter of the compiler. This picture represents a placement in Cyclone FPGA

Mar. 12, 2009Wu, Jinyuan Fermilab31 A 96 Channel TDC Module Data Concentration FPGA 48CH TDC FPGA

Mar. 12, 2009Wu, Jinyuan Fermilab32 The 96 CH TDC Module Specifications

Mar. 12, 2009Wu, Jinyuan Fermilab33 Some Important Details on Coarse Time Counters Connecting coarse time with the fine time is normally considered a “challenge”.

Mar. 12, 2009Wu, Jinyuan Fermilab34 Issues of Coarse Time Counter There are some common misunderstandings on coarse time counters in a TDC: –Tow coarse time counters are needed, driven by clocks with 180 degree phase difference. –The coarse time counter should be a Gray code counter. Actually, dual counters and/or Gray code counters are only needed in one ASIC TDC architecture. In the architectures used by FPGA TDC and some ASIC TDC, only one plain binary counter is needed as coarse time counter. Coarse Time Counter Coarse Time Counter Coarse Time Counter Gray Code Counter

Mar. 12, 2009Wu, Jinyuan Fermilab35 Delay Line Based TDC Architectures HIT CLK HIT CLK HIT CLKHIT CLK Delay HitDelay CLKDelay Both CLK is used as clock HIT is used as clock Only this architecture needs dual coarse time counters.

Mar. 12, 2009Wu, Jinyuan Fermilab36 Implementation of Coarse Time Counter Coarse Time Counter Fine Time Encoder In CLK ENA Fine Time Coarse Time Data Ready Hit Detect Logic

Mar. 12, 2009Wu, Jinyuan Fermilab37 Differential Inputs and Multiple Thresholds An FPGA can handle many differential inputs and each input can feed a TDC functional block. Multi-threshold approach is commonly used to compensate time-walk due to amplitude variation.

Mar. 12, 2009Wu, Jinyuan Fermilab38 Differential Dual Threshold for PMT T0 = (T1+T2)/2 – ((T3+T4)/2-(T1+T2)/2)/4 Four comparators: two for +- signals, two for signals vs. fix thresholds. Insensitive to amplitude, threshold voltage, common mode noise. High resolution TDC is needed only for T1 and T2, not T3 and T4. T3 T0 T4 T1 T2 2Vth8Vth T1 T2 T3 T4

Mar. 12, 2009Wu, Jinyuan Fermilab39 Insensitivity to Common Mode Level T3 T0 T4 T1 T2 2Vth 8Vth T0 = (T1+T2)/2 – ((T3+T4)/2-(T1+T2)/2)/4 Typically, differential noise << common mode noise. The common mode level variation is canceled in (T3+T4). Large common mode noise is tolerated.

Mar. 12, 2009Wu, Jinyuan Fermilab40 Another Differential Dual Threshold Input Circuit T3 T0 T1 T2 8Vth T1 T2 T3

Mar. 12, 2009Wu, Jinyuan Fermilab41 Summary FPGA TDC covers wide range of applications: –TOF, Delta T RMS resolution: 20-25ps: Delay Line. –Drift Chamber, LSB 0.5-1ns: Multi-sampling. After-fact digital calibration instead of analog compensation is more convenient for FPGA TDC. Multiple-measurement method is used in the Wave Union TDC to improve performance.

Mar. 12, 2009Wu, Jinyuan Fermilab42 The End Thanks

Mar. 12, 2009Wu, Jinyuan Fermilab43 TDC Back End

Mar. 12, 2009Wu, Jinyuan Fermilab44 Calibration Resource

Mar. 12, 2009Wu, Jinyuan Fermilab45 Timing Diagram

Mar. 12, 2009Wu, Jinyuan Fermilab46 “Wavelet TDC” --> “Wave Union TDC” This design was named “Wavelet TDC”. Criticism was received for confusion that may be caused by using “Wavelet”. It is now renamed as “wave union” TDC.

Mar. 12, 2009Wu, Jinyuan Fermilab47 Wave Union Launcher B: Delta T Plain TDC: –delta t RMS width: 40 ps. –25 ps single hit. Wave Union TDC B: –delta t RMS width: 12 ps. –8 ps single hit. Wave Union TDC B (+) Random Input

Mar. 12, 2009Wu, Jinyuan Fermilab48 FPGA and ASIC FPGA is not the best vehicle to pursue the resolution frontier. (Double-digit ps). However, some tricks can be cross- transplanted between FPGA & ASIC: –Multi-measurement method. –Auto calibration to eliminate PLL and to tolerate DNL as silicon process goes finer.

Mar. 12, 2009Wu, Jinyuan Fermilab49 Delay Line in ASIC TDC  Encoder Auto Calibration

Mar. 12, 2009Wu, Jinyuan Fermilab50 The End Thanks