© 2004 Xilinx, Inc. All Rights Reserved EDK Overview

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Objectives After completing this module, you will be able to: Describe the embedded systems development flow Understand the components in the hardware design Specify ways to create a hardware design Identify the tools included in the EDK Locate the EDK documentation List the supported operating systems

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Embedded Systems An embedded system is nearly any computing system (other than a general-purpose computer) with the following characteristics – Single-functioned Typically, is designed to perform predefined function – Tightly constrained Tuned for low cost Single-to-fewer components based Performs functions fast enough Consumes minimum power – Reactive and real-time Must continually monitor the desired environment and react to changes – Hardware and software co-existence

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Embedded Systems Examples: – Mobile phone systems Customer handsets and base stations – Automotive applications Braking systems, traction control, airbag release systems, and cruise-control applications – Aerospace applications Flight-control systems, engine controllers, auto-pilots and passenger in-flight entertainment systems – Defense systems Radar systems, fighter aircraft flight-control systems, radio systems, and missile guidance systems

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Current Technologies Microcontroller-based systems DSP processor-based systems ASIC technology FPGA technology

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO (4K & Virtex  ) Embedded Software Tools CPU Integration of Functions Time Logic Design Tools Embedded Software Tools Logic + Memory + IP + Processors + RocketIO (Virtex-II Pro  ) Programmable Systems usher in a new era of system design integration possibilities Programmable Systems usher in a new era of system design integration possibilities Integration in System Design

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Embedded Design in an FPGA Embedded design in an FPGA consists of the following: – FPGA hardware design – C drivers for hardware – Software design RTOS versus Main + ISR

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PowerPC 405 Core Dedicated Hard IP Flexible Soft IP RocketIO PowerPC-based Embedded Design Full system customization to meet performance, functionality, and cost goals DCR Bus UART GPIO On-Chip Peripheral Hi-Speed Peripheral GB E-Net e.g. Memory Controller Arbiter On-Chip Peripheral Bus OPB Arbiter Processor Local Bus InstructionData PLB DSOCM BRAM ISOCM BRAM Off-Chip Memory ZBT SSRAM DDR SDRAM SDRAM Bus Bridge IBM CoreConnect™ on-chip bus standard PLB, OPB, and DCR

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only MicroBlaze-based Embedded Design Flexible Soft IP MicroBlaze  32-Bit RISC Core UART 10/100 E-Net On-Chip Peripheral Off-Chip Memory FLASH/SRAM LocalLink™ FIFO Channels 0,1…….32 Custom Functions Custom Functions BRAM Local Memory Bus D-Cache BRAM I-Cache BRAM Configurable Sizes Possible in Virtex-II Pro Arbiter OPB On-Chip Peripheral Bus

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Embedded Development Tool Flow Overview Data2MEM Bitstream Compiler/Linker (Simulator) C Code Debugger Standard Embedded SW Development Flow CPU code in on-chip memory ? CPU code in off-chip memory Download to Board & FPGA Object Code Standard FPGA HW Development Flow Synthesizer Place & Route Simulator VHDL/Verilog ? Download to FPGA

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only EDK The Embedded Development Kit (EDK) consists of the following: – Xilinx Platform Studio – XPS – Base System Builder – BSB – Creating/Importing IP Wizard – Hardware generation tool – PlatGen – Library generation tool – LibGen – Simulation generation tool – SimGen – GNU software development tools – System verification tool – XMD – Processor IP – Drivers for IP – Documentation Use the GUI or the shell command tool to run the EDK tool

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only EDK Processor IP MPD Files system.ucf system.bit MHS File system.mhs PlatGen ISE/Xflow Hardware Data2MEM download.bit Compile Link Object Files Executable Libraries Source Code LibGen MSS File system.mss EDIF IP Netlists Source Code Synthesis

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Platform Studio Source Code Editor System Diagram View System Details View Integrated Hardware and Software System Development Tools

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only XPS Functions XPS HW/SW Simulation HW/SW Debug Hardware Design Software Design Project management – MHS or MSS file – XMP file Software application management Platform management – Tool flow settings – Software platform settings – Tool invocation – Debug and simulation

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Management Create a new project – Using Base System Builder – Using Platform Studio – New Project toolbar button Opens a Platform Studio GUI Open an existing project – Import existing MHS file – Select the Target Device – Specify a single Peripheral Repository Project information is saved in the Xilinx Microprocessor Project (XMP) file

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Create a Project Using Base System Builder (BSB) Select a target board Select a processor Configure the processor Select and configure I/O interfaces Add internal peripherals Generate the system software and the linker script Generate the design – system.mhs – data/system.ucf – etc/fast_runtime.opt – etc/download.cmd – system.bsb (optional, if selected) – TestApp/src/TestApp.c (optional, if selected) – TestApp/src/TestAppLinkScr (optional, if selected)

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Using BSB Identify Location and Project File Name 1 Select a Board Vendor, Name, and Revision 2 Alternatively, you can start with an already built project and make changes 2A

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Using BSB Select a processor 3 Configure the processor and bus speeds, and debug 4

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Using BSB Select and configure I/O 5 Add internal peripherals 6 Number of peripherals displayed will depend on the screen size and resolution 5A

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Using BSB Configure software application and linker script 7 Assign stdin and stout devices if present 7A Assign memory blocks for various purposes Assign memory blocks for various purposes 7B Deselecting this option will not generate software application and linker script Deselecting this option will not generate software application and linker script 7C

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Using BSB Generate the system 8

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Through Platform Studio Identify Location and Project File Name 1 Identify Target Device 2 or

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Through Platform Studio Select modules from the catalog and click Add to instantiate them in your design 3 Select and Edit the Address Map for Each Module 4

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Creation Through Platform Studio Identify the bus to which modules are attached as Slave or Master 6 Add buses to the project 5

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Software Application Management XPS supports test application creation and linker script management through BSB XPS allows users to specify multiple application projects in the Applications tab XPS has an integrated editor for viewing and editing the C source and header files of the user program The source code is grouped for each processor instance. You can add or delete the list of source code files for each processor All of the source code files for a processor are compiled by using the compiler specified for that processor XPS tracks changes to C/C++ source files and recompiles when necessary

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Process Management Platform management tasks of XPS include – Librarie and device driver configuration (LibGen) – Simulation model generation (SimGen) – Implementation (Xflow or ISE) – Compilation (GNU Compiler) – Bitstream initialization (Data2MEM) To change the system specification and software settings, XPS supports the following features and processes – Add/Edit Cores (Dialog) – Software Platform Settings – Tool Flow Settings – Tool Invocation

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Add/Edit Cores (Dialog) Design and modify the hardware system – Add peripherals Processor: PowerPC  or MicroBlaze  Bus: PLB, OPB, OCM Add bus-specific IP Customize IP – Delete peripherals Processor Bus-specific IP Custom IP – Change (add/delete/modify) settings Base address and end address Parameters Ports

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Software Platform Settings Used to set all the software platform related options in the design Has multiple tabs – Software Platform Drivers Libraries Kernel and Operating Systems – Processor and Drivers Parameters Compilers Core clock frequency – Library/OS Parameters Stdin and stdout devices Malloc function usage option

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Options Settings XPS supports project options settings for – Device and Repository – Hierarchy and Flow – Simulation

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Options Device and Repository Tab Set/Change Target Device – Architecture – Device Size – Package – Grade Peripheral Repository Directory – Provide path to custom IP not present in the current project directory structure Custom Makefile Directory Note: Detailed information on the other two tabs is provided in the Adding Your Own IP to the OPB Bus module and the System Simulation module

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware Design Example We will build the following system from scratch (while no components are present in the system) We will start with Project  Add/Edit Cores … (Dialog) PLB Bus OPB Bus PLB BRAM INTC Timer GPIO UART MY IP GPIO PLB2OPB PLB BRAM Cntlr PLB BRAM Cntlr PPC

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Add/Edit Cores Peripherals Tab In XPS, select Project  Add/Edit Cores... to open the System Settings dialog Select one or more cores to be included into the system MHS file, then click << Add

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Embedded Design Progress Having placed the processor and peripherals, add buses PPC PLB Bus PLB2OPB PLB BRAM Cntlr OPB Bus PLB BRAM Cntlr PLB BRAM INTC Timer GPIO UART MY IP GPIO

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Add/Edit Cores Bus Connections Tab Select and add the buses required in the system Specify the bus to which each peripheral is connected as master or slave Specify the BRAMs to the correct Memory Controllers

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware Design Progress Having assigned bus connections, connect internal and external ports PPC PLB Bus PLB2OPB PLB BRAM Cntlr OPB Bus PLB BRAM Cntlr PLB BRAM INTC Timer GPIO UART MY IP GPIO

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Add/Edit Cores Ports Tab Filter ports by instance or string Add/Remove ports to be connected Connect component ports using nets and Specify net names Specify if a net is internal or external Specify net sizes

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Defining a Connection Select ports to be connected (use Shift or Ctrl keys) Click Connect Enter the net name used for the connection Specify whether a net is internal or external

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware Design Progress RSTC405RESETCORE RSTC405RESETSYS C405RSTCHIPRESETREQ RSTC405RESETCHIP C405RSTCORERESETREQ C405RSTSYSRESETREQ PowerPC Processor System Reset JTAG PPC JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TDO JTGC405TDOEN JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TDO JTGC405TDOEN RSTC405RESETCORE RSTC405RESETSYS CHIP_RESET_REQ RSTC405RESETCHIP CORE_RESET_REQ SYSTEM_RESET_REQ Once ports are connected, each device can be configured for specific functionalities

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Add/Edit Cores Parameters Tab Define the IP Peripheral parameters for each core Default values are shown Overriding values can be entered Default values Overriding values

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only EDK Libraries system.ucf system.bit ISE/Xflow Hardware Data2MEM download.bit Compile Link Object Files Executable Source Code LibGen MSS File system.mss EDIF IP Netlists Source Code Synthesis Processor IP MPD Files MHS File system.mhs PlatGen Focus Here

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware Design Platform Generator (PlatGen) inputs the following files: – MHS file – MPD file PlatGen constructs the embedded processor system in the form of hardware netlists (HDL and implementation netlist files) MHS file parameters override the MPD parameters – The MPD parameters are the defaults

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Hardware Design Microprocessor Peripheral Definitions File Microprocessor Hardware Specification File MHS overrides MPD MPD contains all of the defaults

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PlatGen HDL directory – system.[vhd|v] file (if top-level) – system_stub.[vhd|v] file (if sub-module) – peripheral_wrapper.[vhd|v] files Implementation directory – peripheral_wrapper.ngc files – system.ngc file – system.bmm file Synthesis directory – peripheral_wrapper.[prj|scr] files – system.[prj|scr] files project_directoryhdl directoryimplementation directory PlatGen Generated Directories synthesis directory

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PlatGen Memory Generation Memory generation – Platform Generator generates the necessary banks of memory and the initialization files for the BRAM block (bram_block). The BRAM block is coupled with a BRAM controller – Current BRAM controllers include the following: DSOCM BRAM Controller (dsbram_if_cntlr) ISOCM BRAM Controller (isbram_if_cntlr) PLB BRAM Controller (plb_bram_if_cntlr) OPB BRAM Controller (opb_bram_if_cntlr) LMB BRAM Controller (lmb_bram_if_cntlr)

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only PlatGen Memory Sizes Memory sizes Memory must be built on 2n boundaries – Let n be the number of address pins on the memory, and let I be the unsigned number formed by the starting address or memory size. If I is the integer, then the memory is built on the 2n boundary – One-KB memory at $4000 is at the 2n boundary; whereas, one KB at $4100 is not PLB Bus OPB, LMB, OCM Buses

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only BlockMemory Map A BMM (BlockRAM Memory Map) file contains a syntactic description of how individual BlockRAMs constitute a contiguous logical data space PlatGen has the following policy for writing a BMM file: – If PORTA is connected and PORTB is not connected, then the BMM generated will be from PORTA point of reference – If PORTA is not connected and PORTB is connected, then the BMM generated will be from PORTB point of reference – If PORTA is connected and PORTB is connected, then the BMM generated will be from PORTA point of reference

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction EDK – Project Management – Software Application Management – Platform Management Hardware Design PlatGen Supported Platforms

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Supported Platforms Operating systems – Windows 2000  (Service Pack 2) – Windows XP  – Solaris  2.8/2.9 – Linux Red Hat FPGA families – Spartan  -II (MicroBlaze  ) – Spartan-IIE (MicroBlaze) – Spartan III (MicroBlaze) – Virtex  and Virtex E (MicroBlaze) – Virtex-II (MicroBlaze) – Virtex-II Pro  (MicroBlaze and PowerPC  )

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only BSB Supported Platforms Some of the Hardware boards – Avnet  Virtex-II Pro  Development Board – Avnet  Spartan  -III Evaluation Board – Memec design Spartan  -IIE Development Boards – Memec design Virtex-II MicroBlaze  Development Board – Memec design Virtex-II Pro  Development Boards – Xilinx Spartan  -III Starter Board – Xilinx ML300  board – Xilinx ML310  board Others available from the Board Vendor

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Skills Check

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Review Questions What is the smallest memory size that PlatGen can generate for a Spartan  -IIE device? Why is the address 0xFFFF_B100, NOT a valid BASEADDR for a LMB BRAM controller? What will the BAUDRATE for the peripheral be: – If the MPD has the following parameter: C_BAUDRATE = 9600 – If the MHS has the following parameter: C_BAUDRATE =

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Answers What is the smallest memory size that PlatGen can generate for a Spartan  -IIE device? – 2 KB Why is the address 0xFFFF_B100, NOT a valid BASEADDR for a LMB BRAM Controller? – It is not on a 2n boundary What will the BAUDRATE for the peripheral be: – If the MPD has the following parameter: C_BAUDRATE = 9600 – If the MHS has the following parameter: C_BAUDRATE =

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Memory Space How do you build a 48-KB OPB BRAM memory space for a MicroBlaze  processor in a Virtex  -II device? ? KB 0x 0x0000_0000 0x

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Memory Space How do you build a 48-KB OPB BRAM memory space for a MicroBlaze  processor in a Virtex  -II device? 32 KB 16 KB 0x0000_7FFF 0x0000_0000 0x0000_8000 0x0000_BFFF

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Memory Requirement How many block RAMs do you think will be used to build a 16-KB PLB memory space for a PowerPC  processor in a Virtex-II Pro  device? And why?

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Memory Requirement How many block RAMs do you think will be used to build a 16-KB PLB memory space for a PowerPC  processor in a Virtex-II Pro  device? And why? – Eight block RAMs will be used – Because PowerPC allows a byte write, the memory is organized in a byte- wide mode. The Virtex-II Pro block RAM has 18 Kb; each block will be configured in 2K x 8. This will require eight block RAMs

EDK Overview © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Where Can I Learn More? Tool documentation – Getting Started with the Embedded Development Kit – Processor IP Reference Guide – Embedded Systems Tools Guide – Xilinx Drivers Processor documentation – PowerPC Processor Reference Guide – PowerPC 405 Processor Block Reference Guide – MicroBlaze Processor Reference Guide Support website – Tech Tips: – EDK Home Page: support.xilinx.com/edk