Status report 2010/10/22 Atsushi Nukariya

Progress ・ Progress is as follows. 1. Confirm to transfer data from SiTCP to PC. 2. Create software which read data. 3. Create function which send command to SiTCP from PC. (Only simulation)

Transfer data (1) ・ Tests need a signal from outside, so I create Data Generator on FPGA. ・ D-Buffer receive signal from Data Generator, instead of signal from GEMFE2 Input. ・ Dataflow is as follows. FPGA Data Generator GEMFE2 Input D-Buffer FIFO SiTCP Output

Transfer data (2) ・ Specification of Data Generator is as follows. Specification of Data Generator Output data Data Generator has 23bits counter, so number of counter is outputted. Once every three times, Empty signal (0x200000) is sent. Clock frequency Operation clock frequency is 20MHz (RCLK). Example of output data 0x0000A1→0x0000A2→0x200000→0x0000A3→ ・・・

Transfer data (3) ・ Specification of Data Generator is as follows. Data from Data Generator ・ It seems that counter on Data Generator doesn’t work correctly, but what I should do now is that data is transferred to SiTCP correctly. So, I don’t care about this problem.

Transfer data (4) ・ I setup SiTCP using SiTCP Utility. SiTCP Utility Function Setting IP address of SiTCP. Displaying data which is transferred from SiTCP.

Transfer data (5) ・ It seems that data is transferred from SiTCP correctly. But sometimes only 0x00 data is sent. (This problem may come from Data Generator ?)

Software (1) ・ I create software which reads data, but this software is prototype, so I need revision. ・ Class diagram is as follows. (This diagram is temporary version.)

Software (2) ・ I created software which sends data to loopback address , and tests process speed. ・ Data which sends loopback address is 0x20 only. (This is Empty flag) ・ Setup is as follows. PC Data sender GEMFE2 software Loopback address ( ) Data : 0x20

Software (3) ・ Result is as follows. Data senderGEMFE2 software Data output transfer rate Data input transfer rate Data process speed Remainder of ring buffer

Software (4) Item Data output transfer rate Output transfer rate to GEMFE2 software. Data input transfer rate Input transfer rate from Data sender. Data process speed Speed which GEMFE2 software process data. Remainder of ring buffer Value which reading pointer is subtracted from writing pointer. This value must be some constant value. (If this value isn’t constant, ring buffer will be full. )

Software (5) ・ I know this status is bad. → Ring buffer will be full. → Packet loss will occur. ・ Next step is as follows. Next step Revise algorithm Send command to SiTCP If ring buffer seems to be full, signal which stops FPGA function is sent from GEMFE2 software.

Send command (1) ・ I’m creating CommandSender class. This class inherits Thread class. ・ Thread class which I made has a function which make another thread. Thread Command Sender SockThread

Send command (2) ・ I also add function of FPGA. FPGA Control Manager SiTCP Input Command

Send command (2) ・ Result of simulation is as follows. ・ LED represents status of FPGA. ・ Data is sent correctly. Output data LED 0b STOPSTART

Send command (3) ・ Status of FPGA is as follows. LED STATE_RESET LED is 0b STATE_CONFIGURE LED is 0b STATE_WAIT LED is 0b STATE_STOP LED is 0b STATE_TRANSFER LED is 0b STATE_UNKNOWN LED is 0b

Next plan ・ Test whether FPGA works correctly. ・ Measurement of SiTCP’s transfer rate. ・ Revise software. ・ Add function of FPGA. Etc...