Design Methodology 1 Design Methodology for High-Density FPGA Design Selecting an Architecture High-Density Software Methodology Implementation and Integration of Cores

Design Methodology 2 Spread Spectrum Frequency Channel Allocation Design PCI Channel Manager Transmitter Channel Interface A/D V400 FPGA CPU and Software Spectral Analysis System Level FPGA

Design Methodology 3 Challenges of High-Density FPGA Design  How to Implement? Architecture  What Architecture?  Software  Software Access to Architectural Features?  Verification Strategy  Verification Strategy? IP Cores  Use IP Cores? PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis

Design Methodology 4 Agenda  Selecting an architecture —system level FPGA —Smart-IP technology  High-density FPGA software methodology —design flow —accessing the architecture specific features —design verification  Implementation and integration of cores —CORE Generator —LogiCORE —AllianceCORE —design series  Software demo  Roadmap

Design Methodology 5 System-Level FPGA PCI Channel Manager Transmitter Channel Interface A/D CPU and Software Spectral Analysis  Integrates with software tools?  High performance I/O standards?  Million system gates?  Performance? —100 MHz  Memory? —SRAM, FIFO  IP friendly? —133 MHz SDRAM 1 Gbit Ethernet 66 MHz PCI

Design Methodology 6 Only available from Xilinx Xilinx Smart-IP Technology  Xilinx Smart-IP Technology —architectures tailored to cores —intelligent software implementation —flexible core technology  Delivers: —high predictability —high performance —high flexibility

Design Methodology 7 Xilinx Smart-IP Technology Architecture Tailored to Accept Cores Advantages Efficient Routing Predictable Timing Low Power Xilinx Segmented RoutingNon-Segmented Routing Core1 Core2

Design Methodology 8 Advantages Portable RAM-based cores 16x improved logic efficiency High-performance cores Local RAM available to the Core Distributed Memory Xilinx Smart-IP Technology Architecture Tailored to Accept Cores

Design Methodology 9 Enhances Performance & Predictability Relative Placement Other Logic Does Not Affect on the Core Fixed Placement & Pre-defined Routing Guarantees Performance Guarantees I/O & Logic Predictability Fixed Placement I/Os Xilinx Smart-IP Technology Pre-defined Placement & Routing

Design Methodology 10 Performance is independent of core placement and number of cores used in the device Avoids the performance loss of non-segmented architectures Xilinx Smart-IP Technology Delivers Design Predictability 80 MHZ

Design Methodology 11 Performance is independent of device size Xilinx Smart-IP Technology Delivers Design Predictability Avoids the performance loss of non-segmented architectures

Design Methodology 12 Virtex Enables PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis Integrates with software tools? High performance I/O standards? Million system gates? Performance? —100 MHz Memory? —SRAM, FIFO IP friendly? —133 MHz SDRAM 1 Gbit Ethernet 66 MHz PCI System Level FPGA

Design Methodology 13 Agenda Selecting an architecture —system level FPGA —Smart-IP technology  High-density FPGA software methodology —design flow —accessing the architecture specific features —design verification  Implementation and integration of cores —CORE Generator —LogiCORE —AllianceCORE —design series  Software demo  Roadmap

Design Methodology 14 The Value of Xilinx Partnerships The most comprehensive “Open System” solution  Early software support for new devices  New product development maximizing architectural and synthesis capabilities –efficient timing constraints integration –high performance optimization engines tuned for new Xilinx devices –direct optimization & mapping of Carry logic, complex I/O, LUTs, CE, arithmetic operator  Joint definition of next-generation Solutions

Design Methodology 15 Design Verification Design Implementation Design Entry Source Code Design Flow Functional Simulation Timing Simulation Top Level HDL or Schematic Netlist Symbol/HDL Synthesis User design only Netlist Sim.Model Constraints Netlist Place & Route HDL Editor Design Reuse AllianceCORE LogiCORE Schematic Entry Static Timing Analysis Xilinx FPGA

Design Methodology 16 XC4000XL family supported in A1.5, Virtex to follow Software Features (ASIC-Like)  Minimum-delay reporting —hold-time analysis —finds hazards in asynchronous logic —min delay option “-s min” for TRCE and NGDANNO  Voltage and temperature pro rating —can specify a higher voltage than worst case –specify 3.3V instead of 3.0V —can specify a lower temperature than worst case –specify 55°C instead of 85°C  First SRAM based device to support temp & voltage pro rating and minimum delays

Design Methodology 17 Minimum Delay System-Level Analysis  Internally, Xilinx guarantees 0ns hold times  Identify board-level hold time violations for synchronous designs System Clock Inst_A Q System Clock FPGA SDRAM Flip-Flop Hold time 1 ns D System Clock With max tco (for Inst_A) = 5 ns With min tco (for Inst_A) = 2 ns Q Q Valid data on Q for worst case delay D D Hold Time violation for best case delay 1 ns Data not latched } }

Design Methodology 18 Temperature and Voltage Pro rating  Delays based on worst case process  Adjust temperature and voltage to reflect system operating conditions  Reduce system cost by targeting a slower speed grade Parameter [ns] Internal Period Clock-to-Out Input Setup Parameter [ns] Internal Period Clock-to-Out Input Setup System Requirements 3.3V, 70°C System Requirements 3.3V, 70°C XLA–08 V = 3.0V T = 85°C XLA–08 V = 3.0V T = 85°C XLA–08 V = 3.3V T = 70°C XLA–08 V = 3.3V T = 70°C Meets Requirements XLA–09 V = 3.3V T = 70°C XLA–09 V = 3.3V T = 70°C Lowest Cost

Design Methodology 19 1 Million Gates In Less Than 5 Hours Compile Times Gates Per Hour 150k 100k 50k 0 200k A 1.5 XC4000XL A 1.5 Timing Driven Implementation 50k Gates / hour 35k Gates / hour A 1.4 XC4000XL  New place & route algorithms  Abundant & flexible vector based interconnect —4x routing resource vs XC4000XL —fully populated switch matrix  Buffering of high fanout and long distance interconnects —8 ns across 250K system gates  Up to 40% smaller interface netlist 200k Gates/ hour

Design Methodology 20 Faster Compiles with Virtex “ Tough” Customer Designs Compile Time (minutes) Virtex compiles, on average, 28 times faster Virtex -4 XC4000XL-09 Design Suite

Design Methodology 21 Faster Systems with Virtex “ Tough” Customer Designs 0 100% 200% Design Suite Normalized Clock Speed  Faster Virtex speeds with silicon characterized speeds files  Virtex is faster for 84% of the designs  Designs from ATM, PCI, Networking & ISDN applications 19 Virtex -4 XC4000XL-09

Design Methodology 22 Accessing Technology-Specific Features  By inference —technology mapping using behavioral constructs that allow code portability —operators —RAM  By instantiation —use gates in the target technology making the code technology specific —Block RAM —CLKDLL —special I/Os.

Design Methodology 23 Inferring Technology-Specific Features  Fast arithmetic carry chains  Wide input muxes, “case vs. priority encoder”  RTL flexibility for register configurations  Area-efficient muxes using TBUFs  Distributed RAM inferencing  Registered I/O buffer inference  Timing-driven register IOB mapping

Design Methodology 24  180 MHz 32-bit arithmetic/counters  Small 16-bit adders using 16 LUTs —51 for XC4000XL  60MHz 16x16 multipliers —30% area reduction compared to XC4000XL —160MHz with pipeline stages  Operator Inferencing from synthesis  Pipelined multipliers from the CORE Generator tool Virtex Logic Block Carry Fast Arithmetic Functions Using Carry Chains if (!reset) count = 32’b0; else count = count + 1’; Sum = a_in + b_in mult = a_in * b_in LUT

Design Methodology 25 in [4] S S S S in [2] in [1] in [0] in [3] Priority Encoder “if-then-else” When to use?  Assign highest priority to a late arriving critical signal  Nested “if-then-else” might increase area and delay  Use “case” statement if possible to describe the same function or in) begin if (sel == 3'h0) out = in[0]; else if (sel == 3'h1) out = in[1]; else if (sel == 3'h2) out = in[2]; else if (sel == 3'h3) out = in[3]; else if (sel == 3'h4) out = in[4]; else out = in[5]; end

Design Methodology 26 Benefits of “Case” Statement C D E F G H I J S Z 8:1 Mux  Compact and delay-optimized implementation —implemented in a single CLB  Synthesis maps to MUXF5 and MUXF6 functions  8:1 multiplexor is implemented in a single CLB or D or E or F or S) begin case (S) 2’b000 : Z = C; 2’b001 : Z = D; 2’b010 : Z = E; 2’b011 : Z = F; 2’b100 : Z = G; 2’b101 : Z = H; 2’b110 : Z = I; default : Z = J; endcase

Design Methodology 27  Register mapping for —registers with sync/async set and reset —clocks, inverted clocks, and clock enable Positive-Edge Triggered Flip-Flop with clock enable, sync reset and preset reset data clk q preset ce clk or posedge preset) begin if (preset) q = 1; else if (reset) q = 0; else if (CE) q = data; end RTL Flexibility for Register Configurations

Design Methodology 28 Area Efficient Muxes Using TBUFs  Improve area efficiency by using tri-states  Each CLB has 2 TBUFs  Place-and-route can connect tri-states on multiple horizontal Longlines to build wide muxes E[3:0] A[7:0] B[7:0] C[7:0] D[7:0] Z[7:0] A[7:0] B[7:0] C[7:0] D[7:0] E0 E1 E2 E3 Z[7:0] case (E) 4’b0001 : Q[7:0] = A[7:0]; 4’b0010 : Q[7:0] = B[7:0]; 4’b0100 : Q[7:0] = C[7:0]; 4’b1000 : Q[7:0] = D[7:0]; endcase assign Q[7:0] = E0 ? A[7:0] : 8'bzz..z; assign Q[7:0] = E1 ? B[7:0] : 8'bzz..z; assign Q[7:0] = E2 ? C[7:0] : 8'bzz..z; assign Q[7:0] = E3 ? D[7:0] : 8'bzz..z;

Design Methodology 29 Distributed RAM Inferencing System Memory Synplicity (RAM 8x4)  Synplify and Leonardo Spectrum can infer distributed RAM  FPGA Express will support RAM inferencing in the future AO A1 A2 A3 D WCLK WE Addr [2:0] D [3:0] clk we q [3:0] RAM 16x1S Q module ramtest(q, addr, d, we, clk); output [3:0] q; input [3:0] d; input [2:0] addr; input we; input clk; reg [3:0] mem [7:0]; assign q = mem[addr]; clk) begin if(we) mem[addr] = d; end endmodule AO A1 A2 A3 D WCLK WE

Design Methodology 30 Registered I/O Mapping System Interfaces  System timing —chip-to-chip performance often limits system speeds —registered I/O improves performance  No need to instantiate IOB register cells —implementation tools will pack registers in the IOBs —map -pr b –b (both input and output) –i (input only) –o (output only) —IOB = TRUE attribute  Mapping for data and enable ports S/R D CE CLK Q OBUF S/R Q CE D CLK IBUF S/R D CE CLK Q OBUF

Design Methodology 31 Controlling the Inference of Output Registers  Technology mapping will not duplicate registers  Critical signal will not be absorbed in the IOB register OUT [23:0] TRI TRI_R CLK DQ DATA [23:0] fanout = 24 process (Tri, Clk) begin if (clk’event and clk =`1`) then Tri_R <= Tri; end if; end process; process (Tri, Data_in) begin if (Tri_R = ‘1’) then Out <= Data_in; else Out ‘Z’); end if; end process;

Design Methodology 32 Controlling the Inference of Output Registers  Duplicates register on critical path for fanout of 1  Mapping will absorb register in IOB TRI CLK DQ TRI_R1 DATA [23] OUT [23] fanout = 1 TRI CLK D Q TRI_R2 OUT [22:0] DATA [22:0] fanout = 23 process (Tri_, Clk) begin if (clk’event and clk =`1`) then Tri_R1 <= Tri; Tri_R2 <= Tri; end if; end process; process (Tri_R1, Data_in) begin if (Tri_R1 = ‘1’) then Out(23) <= Data_in(23); else Out(23) <= ‘Z’); end if; end process; process (Tri_R2, Data_in) begin if (Tri_R2 = ‘1’) then Out(22:0) <= Data_in(22:0); else Out(22:0) ‘Z’); end if; end process;

Design Methodology 33 Instantiating Technology-Specific Features  Block RAM —system memory  CLKDLL —minimizes clock skew  Special I/Os —interfacing with standard buses  LUTs for datapath pipelining —add latency with minimal area impact

Design Methodology 34 RAMB4_S1 do DO addr en we rst clk di ADDR WE EN RST D CLK Block RAM System Memory component RAMb4_S1 port(WE,EN,RST,CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(11 downto 0); DO: out STD_LOGIC; DI: in STD_LOGIC_VECTOR(0 downto 0)); end component; begin U1: RAMB4_S1 port map(WE=>WE, EN=>EN, RST=>RST, CLK=>CLK, DI=>DI, ADDR=>ADDR, DO=>DO); RAMB4_S1 U1 (.WE(WE),.EN(EN),.RST(RST),.CLK(CLK),.ADDR(ADDR),.DI(DI),.DO(DO));  Instantiate single- and dual-port RAM  Use the CORE Generator to build RAM and FIFO (Q1 ‘99)

Design Methodology 35 Verilog BUFG CLKIN CLKFB RST CLKDLL CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED IBUFG U4 clkin rst clk_fb CLKDLL Minimize Clock-to-Out System Timing  One use of a CLKDLL is to minimize clock to outpad delay —removes all delay from external GCLKPAD pin to the registers and RAM  BUFGDLL is available for instantiation  Other configurations can be built by instantiating the CLKDLL macro wire clk_fb; BUFGDLL U4 (.I(clkin),.O(clk_fb));

Design Methodology 36  Default I/O buffer is LVTTL (12mA), available via inference —process technology leads to mixed voltage systems —high-performance, low-power signal standards emerging  Instantiate I/O buffers for non default current drive —non-default voltage standard —non-default slew  Advanced Graphics Port bus interface (Pentium II graphics app)  Fast slew rate and 24 mA drive strength OBUF_AGP U0 (.I(awire),.O(oport)); OBUF_F_24 U1 (.I(awire),.O(oport)); awire oport U0 awire oport U1 Special I/O Buffers System Interfaces

Design Methodology 37 LUTs for Datapath Pipelining  LUT can be used in place of registers to balance pipeline stages —area efficient implementation  SRL16E can delay an input value up to 16 clock cycles  Synchronized operands before the next operation F G H A[31:0] B[31:0] C[31:0] Z 8 cycles 5 cycles 1 cycle SRL16E D CE CLK A3 A2 A1 A0 Q 7 SRL16E D CE CLK A3 A2 A1 A0 Q LUTs replace 256 registers 32 LUTs replace 416 registers

Design Methodology 38 Design Verification  Trends  Stages  Xilinx solutions

Design Methodology 39 What’s Driving the Verification Trends? Functional simulation should eliminate 95% of the bugs Design Cycle Stages Functional Simulation SynthesisPAR System Test End Product Cost of Design Error Over Time $$$ 10,000X 1000X 100X 10X 1X

Design Methodology 40 Stages to Verify the Design Synthesis VHDL or Verilog Implementation Gate-level Functional Simulation  Checks the synthesis implementation to gates  Test initialization states  Analyze ‘don’t care’ conditions Gate-level Timing Simulation  Post implementation timing simulation  Test race conditions  Test set-up and holds violations based on operating conditions Gate-level Functional Simulation  Create testbench  Verifies syntax & functionality  Majority of design cycle time  Errors found are inexpensive to fix testbench

Design Methodology 41 UNISIM Library SIMPRIM Library 4 Simulation What Does Xilinx Provide?  Libraries and interfaces for simulation throughout the design flow —functional simulation with UNISIM —timing simulation with SIMPRIM  Mixed-mode simulation —schematic and HDL  Minimum-delay analysis  Voltage and temperature prorating  Unique VHDL simulation of global set/reset capabilities VHDL or Verilog Synthesis Implementation

Design Methodology 42 Benefits of the Xilinx FPGA Software Development Methodology  ASIC-like design flow and features —open development system —minimum delays and temp pro rating —robust Verification Flow  Improve designer productivity —faster compile times, better performance  Utilizing device resources —technology independence since most technology features are accessible via inference —use techniques to reduce area and increase performance

Design Methodology 43 Agenda Selecting an architecture —system level FPGA —Smart-IP technology High-density FPGA software methodology —design flow —accessing the architecture specific features —design verification  Implementation and integration of cores —CORE Generator —LogiCORE —AllianceCORE —design series  Software demo  Roadmap

Design Methodology 44 Implementation and Integration of Cores IP A B C  PCI  PCMCIA  HDLC  Reed-Solomon  MPEG  T1 Framer  DRAM Controller  DMA  Viterbi Decoder  FIR Filter

Design Methodology 45 High-Density FPGA Design Implementation  Xilinx CORE Generator —reduces time to market —delivers parameterizable cores —optimized using SmartIP technology  LogiCORE products —licensed and supported by Xilinx —highly optimized for Xilinx FPGAs results in best possible performance, area and predictability  AllianceCORE products —licensed and supported by Xilinx’ partners —25 partners provides industry’s widest selection of cores and design expertise  Design services —3rd party and Xilinx design centers —local expertise and services

Design Methodology 46 PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis Xilinx CORE Generator IP Delivery System

Design Methodology 47 Benefits of Using Xilinx Cores Reference Design, Generic Core Complete FPGA Core Solution Design From Scratch Pre-verified Designs Area & Timing Optimized Complete & Flexible Design Little Knowledge of Function Required L Design D Verify V Learn V I Implement I L D 2 Months 9 Months 12 Months

Design Methodology 48 Benefits of Using Xilinx Cores “75% of all new designs will have Cores in them” - Designer feedback from IP usage survey “The high performance of the Xilinx PCI LogiCORE solution combined with the short time to market and flexibility of a programmable FPGA solution, made Xilinx the obvious choice." - Tony Clark, R&D Mgr. - Management Graphics, Inc “By using ‘Design Reuse’ as part of our design consulting services, on average we are able to save our customers weeks” - Tim Smith of Memec Design Services

Design Methodology 49 Data sheets CoreLINX: SystemLINX: Web Mechanism to Download New Cores Third-Party System Tools Directly Linked With Core Generator Parameterized Cores Free Software & Free Cores Included As Part of The Alliance and Foundation Software Packages CORE Generator Delivery System Xilinx Smart-IP Technology

Design Methodology 50 Core Generator Demo

Design Methodology 51 PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis Xilinx LogiCORE

Design Methodology 52 Xilinx LogiCORE  Licensed and supported by Xilinx  Highly optimized for Xilinx FPGAs —module based design flow —best possible performance, area and predictability  Building blocks —can be used as-is, or as foundation for high-level cores —give users access to architectural features through automatic tools (e.g., LUT and memory) —examples: Basic Logic, Arithmetic, Counters, Memories  Standard cores —enable high-performance DSP and PCI applications —use unique implementation techniques to deliver unparalleled performance, area and predictability

Design Methodology 53 A Complete PCI Solution Enables Cost-Effective Designs  Widest range of compliant PCI cores —LogiCORE PCI32 (32-bit, 33 MHz cores) —LogiCORE PCI64 (64/32-bit, MHz cores) —all support fully compliant 0 wait-state burst  Synthesizable bridge designs —reusable PCI bridge design examples  Hot PCI prototyping board - Virtual Computer Corp.  PCI driver development tools and reference drivers - Vireo Software Inc.

Design Methodology 54 Power by The Real-PCI™ 64/66 Solution from Xilinx  Real compliance (PCI v2.2) —based on de-facto industry standard PCI FPGA core —only FPGA solution with guaranteed timing —Compact PCI Hot-Swap friendly  Real flexibility —first 66 MHz PCI core implemented in standard FPGAs  Real performance —full 528 MB/s sustained bandwidth

Design Methodology 55 PCI32 Spartan - Lowest Cost PCI Standard Chip External PLD 7K Gates 7K Gates Logic Component cost 100K units Standard Chip PCI Master I/F XCS20XL-4 TQ144* Solution <$7 PCI Master I/F * Supported devices: XCS20XL XCS30XL XCS40XL Power by $5 $20 $10 $15

Design Methodology 56 Combined Flexibility and Predictability  Only PCI cores for FPGAs with guaranteed timing —including 2ns clock-to-out min timing, and 0 ns hold —FPGA characterized together with core —pre-defined critical placement and routing  First parameterizable PCI core on the web —instant access to new design files  First core with modular architecture —core de-coupled from back-end design —back-end customizable without affecting PCI timing

Design Methodology 57 Design Flow Functional Simulation Timing Simulation Design VerificationCORE ConfigurationDesign Entry User Design HDL or Schematic Netlist Symbol Sim.Model Synthesis User design only CORE Design zip or tar Netlist Constraints Netlist Design Implementation Place & Route

Design Methodology 58 Accelerate Your DSP Processor  Performance of a custom IC  Flexibility of a DSP processor —>10 times the performance —lower cost —lower power  Replaces multiple DSP processors  Replaces DSP building block ICs Implement the cycle intensive algorithms in an FPGA GIGA- MACs/Sec S40 Highest Performance DSP Processor bit FIR Filter Benchmark Virtex

Design Methodology 59 Applications  High performance —data sample rate (> 1MHz) or multiple channels —alternative to multiple DSP processors —alternative to custom ICs  Video, image processing, HDTV, set top boxes —image resizing, enhancement  Data communications, wired & wireless —narrow-band filters, multi-rate filters  Military communications, surveillance, radar, sonar  Data encryption - fast, wide multipliers

Design Methodology 60 A Complete High-Performance Programmable DSP Solution  Spartan, XC4000, Virtex  Design tools and DSP IP —LogiCORE & AllianceCORE —CORE Generator software — Elanix - SystemView - integration  DSP prototyping boards  DSP starter kit  DSP support —DSP FAEs, design services System-Level DSP Modeling Tools DSP Functions

Design Methodology 61 PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis Xilinx AllianceCORE

Design Methodology 62 Program  Partnerships with leading third-party IP providers  Complete programmable logic solutions —proven Xilinx cores —test benches, debug software —hardware evaluation boards  License directly from partner —Xilinx netlist and source code versions —Partner guarantees functionality  Information on the Xilinx web site —

Design Methodology 63 Released Products* Bus Interfaces CAN FireWire (IEEE 1394) I 2 C PCMCIA (2 types) USB (3 types) Communications ATM Cell Assembler ATM Cell Delineation 10/100 Ethernet MAC (2) CRC (10- & 32-bit) DES Engine HDLC (2 types) Reed Solomon T1 Framer UTOPIA (master & slave) Viterbi Decoder Image Processing YUV to RGB Processor Peripherals UARTs (7 types) 2910A (3 types) (2 types) DRAM Controller SDRAM Controller RISC Processors (2 types) Demo Boards & Software (15) *As of January, 1999

Design Methodology 64 Partners* Merged with… G & Associates V *As of January, 1999

Design Methodology 65 PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis Xilinx XPERTS Program X ilinx P rogram for E ngineering R esources from T hird partie S

Design Methodology 66  Xilinx certified consultants  Local design services support —ease the targeting of new architectures —PCI, DSP specialists –Accelerate IP design methodology  Cost advantage —Xilinx optimized solution  Partners in all major cities world wide Xilinx XPERTS Program X ilinx P rogram for E ngineering R esources from T hird partie S

Design Methodology 67 Partner Profile  Specialists in PCI Core customization and integration  DSP specialists —expertise and experience in datacom, telecom, XDSL, networking, video and image processing algorithm designs  Specialists in HDL-based team-based designs and ASIC to FPGA conversions  Details on

Design Methodology 68 Benefits of Xilinx FPGA Design Implementation  Complete programmable logic solutions  Xilinx CORE Generator —pre-verified designs —complete and flexible design —module based design —improved time to market  LogiCOREs - “Expertise without the effort” —Smart IP technology —minimum knowledge of function required —design optimized for speed and area  AllianceCORE IP and XPERTS design services partnerships —Leading providers of third-party IP and design services —Smart IP technology* —world-wide access to expertise *All AllianceCORE modules are optimized for Xilinx

Design Methodology 69 PCI Channel Manager Transmitter Channel Interface A/D Virtex V400 FPGA CPU and Software Spectral Analysis Software Demo Putting It All Together

Design Methodology 70 Software Design Flow Demo

Design Methodology 71 Roadmap  Software  Cores  Web Access and Resources

Design Methodology 72 Major Software Features 2.1  Floorplanning —detailed and modular physical layout (manual or from synthesis) —interface to 3rd party RTL floorplanners  Implementation —place-and-route optimized for modular area constraints —critical timing path optimization within modules —much faster runtime for large designs –Compile million gates under 1.5 hours in 1999 —STAMP models for board-level static timing analysis  Guided iterations for synthesis designs —only changed modules must be re-placed and rerouted —reduces runtime and verification time for unchanged modules

Design Methodology 73 Virtex IP Roadmap

Design Methodology 74 Virtex IP Roadmap

Design Methodology 75 Xilinx IP Center Web-Based Resources  Core solutions —What’s new —IP catalog –LogiCORE –AllianceCORE –reference designs —Products and services —Departments –PCI –DSP –telecom —Tools –Core Generator –PCI configuration demo

Design Methodology 76 High-Density FPGA Leadership Addressing the Challenges Development platforms —SmartIP technology - predictable, high performance, flexible —Modular design - enables “system level FPGA” —Virtex - predictable high speed, high density, fast flexible I/O, RAM Software methodologies —Open development system - joint development, early access —ASIC like design flows - min delays, pro-rate temp, verification flow —Access to device resources - technology independent, optimized for Speed and area —Improved productivity - faster compile times, better performance

Design Methodology 77 High-Density FPGA Leadership Addressing the Challenges Design Implementation —Xilinx CORE Generator - Smart-IP technology, predictable, high performance, flexible, updateable from the Xilinx web site —Complete & Compliant PCI - 64/66MHz, low cost 32/33MHz, synthesizable bridge, prototyping boards & drivers —Complete DSP Solutions - fast, low cost, low power, slew of DSP Cores, system level tools & prototyping boards —AllianceCORE Partnerships - focused on vertical solutions, over 25 partners, over 50 cores, verification tools & prototype boards —Multi-Level Support - expert FAE, 3rd party consulting, XPERTS, Xilinx design center