NS Training Hardware

Print Engine Controller NS9775

Overview Print Engine Controller Module Block Diagram

Print Engine Controller 4 JBIG decoders to support tandem, 4-pass, and monochrome engines Supports synchronous and asynchronous engines Maximum synchronous clock rate is 200 MHz Maximum asynchronous clock rate is 100 MHz JBIG decoders can be bypassed if the image is not compressed Automatic or manual JBIG header processing Maximum horizontal resolution and page width is 2400 dpi and 13.6 inches Output FIFO can hold one line at max resolution 4 DMA independent DMA channels Multiple interrupts available to track the status of a print job through module Supports big or little endian modes on AHB bus

Performance Calculations (Page Per Minute) Monochrome/Tandem printer performance calculation in Pages Per Minutes (PPM) Assumptions horizontal/vertical resolution (h res and v res ) is 2400 dpi x 600 dpi video clock rate (f vclk ) is 100 MHz horizontal/vertical correction factors (h corr and v corr ) are / page size (h size and v size ) is 8.5 in x 11 inches PPM = (f vclk x h corr x v corr x 60 sec) / (h res x v res x h size x v size ) = (100x10 6 x x x 60) / (2400 x 600 x 8.5 x 11) = 22.5 Note, for 4-Pass printers divide the Monochrome/Tandem result by 4

Performance Calculations (AHB Bus Bandwidth) The AHB bus bandwidth requirement for the Tandem engine from previous example is shown next. Bus bandwidth (bytes/sec) = (PPM x h res x v res x h size x v size x 4 planes ) / ( 8bits x 60sec/min) = (22.5 x 2400 x 600 x 8.5 x 11 x 4) / (8 x 60) = Mbytes/sec For 4-pass and monochrome printers, divide the result by 4.

Video PLL & Clock Configuration Variables Reference oscillator clock frequency: f ref (must be between 20 MHz and 40 MHz) PLL frequency: f pll (must be between 400 MHz and 800 MHz) PLL multiplier setting: PLLND PLL divider setting: PLLFS VCO frequency: f vco Clock Generator Divider setting: DVR Determine the horizontal synchronization resolution factor – h res. The minimum for most applications is ¼ pixel. This determines the DVR setting.

Video PLL & Clock Configuration Assumptions The required video pixel clock frequency for this example is 52.8MHz. Formulas f vco = f vclk / h res = 52.8MHz / 4 = 211.2MHz f pll = f vco x PLLFS= 211.2MHz x 2= 422.4MHz f ref = f pll / PLLND = 422.4MHz / 16 = 26.4MHz All of the requirements have been met, f pll is between 400Mhz and 800MHz and f ref is between 20MHz and 4 MHz.

Setup Procedure Async Tandem Printer Take the Print Engine Controller module out of reset. Configure the Video PLL Configuration register to provide the correct video pixel clock rate. Read the Video PLL configuration register to determine if the PLL has locked. This should take approximately 4 milliseconds. Write to the GenConfig register to take the sub-modules out of reset. Setup the buffer descriptors for the 4 image planes in external memory by writing to DmaChNInitBdPtr and DmaChNCurrBdPtr, where N is 0-3. Configure interrupts in the Interrupt Enable register. 1. See example in Hardware Users Guide for more detail.

Setup Procedure Async Tandem Printer Write the image line length, in 16-bit words to the OutputFifoReadyThreshold register. Enable automatic JBIG header processing by writing to the Auto Header Enable register for all 4 JBIG decoders. Configure the Output Fifo Ready Interrupt Control and Status register for all 4 planes. Configure the Print Engine Interface module for asynchronous operation and for all other specific print engine operating characteristics. Configure the Video Vertical Margin and Data register with the paper vertical dimension and margin information. Configure the Video Horizontal Margin and Data register with the paper horizontal dimension and margin information. 1. See example in Hardware Users Guide for more detail.

Setup Procedure Async Tandem Printer Write to the GenConfig register to enable all 4 DMA engines. Wait for the Output FIFO ready interrupt, to indicate a full line has been decoded and placed in the Output FIFO for all 4 planes. Write to the Video Control register to begin printing on all 4 planes. Wait for the all 4 planes to finish printing. This is when all 4 end-of- plane interrupts have been received. 1. See example in Hardware Users Guide for more detail.

Setup Procedure Sync Tandem Printer Take the Print Engine Controller module out of reset. Write to the GenConfig register to take the sub-modules out of reset. Setup the buffer descriptors for the 4 image planes in external memory by writing to DmaChNInitBdPtr and DmaChNCurrBdPtr, where N is 0-3. Configure interrupts in the Interrupt Enable register. Write the image line length, in 16-bit words to the OutputFifoReadyThreshold register. Enable automatic JBIG header processing by writing to the Auto Header Enable register for all 4 JBIG decoders. 1. See example in Hardware Users Guide for more detail.

Setup Procedure Sync Tandem Printer Configure the Output Fifo Ready Interrupt Control and Status register for all 4 planes. Configure the Print Engine Interface module for synchronous operation and for all other specific print engine operating characteristics. Configure the Video Vertical Margin and Data register with the paper vertical dimension and margin information. Configure the Video Horizontal Margin and Data register with the paper horizontal dimension and margin information. Write to the GenConfig register to enable all 4 DMA engines. 1. See example in Hardware Users Guide for more detail.

Setup Procedure Sync Tandem Printer Wait for the Output FIFO ready interrupt, to indicate a full line has been decoded and placed in the Output FIFO for all 4 planes. Write to the Video Control register to begin printing on all 4 planes. Wait for the all 4 planes to finish printing. This is when all 4 end-of- plane interrupts have been received. 1. See example in Hardware Users Guide for more detail.

Sync Printer Timing Diagram The printer provides the clock directly in synchronous mode.

Async Printer Timing Diagram The NS9775 provides the clock in asynchronous mode based on an external crystal and the internal PLL/clock generator. The internal video clock is synchronized to the active edge of hsync.

Hints & Kinks Where can I find the JBIG standard? -The JBIG standard is an ITU specification, ITU-T T.82. -The ITU web site is: