ECS642U Embedded Systems ARM CPU and Assembly Code William Marsh

2 ARM University Program Copyright © ARM Ltd 2013 Acknowledgement Some slides from ARM University Program lab-in-a- box Copyright acknowledged

Outline Aims ARM processor and registers ARM instructions Issues for compilation –Code size  instruction length –Memory use: read or write? –Location Example compilation

Aims Learn to read ARM assembly code in overview Most programmers do not write assembly code but … Reading helpful for –Optimising speed (occasionally) –Debugging Illustrative not comprehensive –Look up opcodes as required

Core Concepts (Recap) Variable – location in memory Code processes –Addresses – get the right variable –Data – get the right value Control flow – if, loops, subroutines –Go to correct address –Branch –… or call / return

ARM Architecture

Microcontroller vs. Microprocessor Both have a CPU Microcontroller has peripherals –Analog –Digital –Timing –Clock generators –Communications point to point network –Reliability and safety

Cortex-M0+ Core

ARM Processor Core Registers

ARM Processor Core Registers (32 bits each) R0-R12 - General purpose, for data processing SP - Stack pointer (R13) –Can refer to one of two SPs Main Stack Pointer (MSP) Process Stack Pointer (PSP) LR - Link Register (R14) –Holds return address when called with Branch & Link instruction (B&L) PC - program counter (R15)

ARM Instructions ARM Architecture

Instruction Set Summary Instruction TypeInstructions MoveMOV Load/StoreLDR, LDRB, LDRH, LDRSH, LDRSB, LDM, STR, STRB, STRH, STM Add, Subtract, Multiply ADD, ADDS, ADCS, ADR, SUB, SUBS, SBCS, RSBS, MULS CompareCMP, CMN LogicalANDS, EORS, ORRS, BICS, MVNS, TST Shift and RotateLSLS, LSRS, ASRS, RORS StackPUSH, POP Conditional branchIT, B, BL, B{cond}, BX, BLX ExtendSXTH, SXTB, UXTH, UXTB ReverseREV, REV16, REVSH Processor StateSVC, CPSID, CPSIE, SETEND, BKPT No OperationNOP HintSEV, WFE, WFI, YIELD

Code Size and Thumb 32 bit processor –Longer addresses –Larger code Thumb and thumb-2 –Most instructions 16 bits –High code density

Load/Store Register ARM is a load/store architecture, so must process data in registers, not memory LDR: load register from memory –LDR, source address STR: store register to memory –STR, destination address

Addressing Memory Offset Addressing –[, ] accesses address + –Base Register can be register R0-R7, SP or PC is added or subtracted from base register to create effective address –Can be an immediate constant –Can be another register, used as index Auto-update –Write effective address back to base register –Pre-indexing –Post-indexing

Example

void redOn(void) { // set red on without changing anything else // LED is actve low PTB->PCOR |= MASK(RED_LED_POS) ; }

Summary Addresses in code Loaded using PC offset addressing Ok to read assembly code