Work in Progress --- Not for Publication 1 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting ITRS ERD/ERM ITWG Working Group FxF Meeting Maturity Evaluation for Selected Emerging Research Memory Technologies Jim Hutchby and Mike Garner - Facilitating Casa Don Guanella – Sala Rossa Room Barza di Ispra (Varese Provence), Italy Wednesday April 7, :00 a.m. – 6:30 p.m.

Work in Progress --- Not for Publication 2 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting  Hiroyugi AkinagaAIST  Tetsuya AsaiHokkaido U.  Yuji AwanoFujitsu  George BourianoffIntel  Michel BrillouetCEA/LETI  Joe BrewerU. Florida  John CarruthersPSU  Ralph CavinSRC  U-In ChungSamsung  Philippe CoronelST Me  Shamik DasMitre  Erik DeBenedictisSNL  Simon Deleonibus LETI  Kristin De MeyerIMEC  Michael FrankAMD  Christian GamratCEA  Mike GarnerIntel  Dan HammerstromPSU  Wilfried HaenschIBM  Tsuyoshi HasegawaNIMS  Shigenori HayashiMatsushita  Dan HerrIBM  Toshiro HiramotoU. Tokyo  Matsuo HidakaISTEK  Jim HutchbySRC  Adrian IonescuETH  Kohei ItohKeio U.  Kiyoshi KawabataRenesas Tech  Seiichiro KawamuraSelete  Rick KiehlU. Minn  Hiroshi KotakiSharp  Atsuhiro KinoshitaToshiba  Franz KreuplQimonda  Nety KrishnaAMAT  Zoran KrivokapicAMD  Phil KuekesHP  Lou LomeIDA  Hiroshi MizutaU. Southampton  Murali Muraldihar Freescale  Fumiyuki NiheiNEC  Dmitri NikonovIntel  Wei-Xin NiNDL  Ferdinand PeperNICT  Yaw ObengNIST  Dave RobertsAir Products  Kaushal SinghAMAT  Sadas ShankarIntel  Thomas Skotnicki ST Me  Satoshi SugaharaTokyo Tech  Shin-ichi TakagiU. Tokyo  Ken UchidaToshiba  Yasuo WadaWaseda U.  Rainer WaserRWTH A  Franz Widdershoven NXP  Jeff WelserNRI/IBM  Philip WongStanford U.  Kojiro YagamiSony  David YehSRC/TI  In-Seok YeoSamsung  In-K YooSAIT  Peter ZeitzoffFreescale  Yuegang ZhangIntel  Victor ZhirnovSRC Emerging Research Devices Working Group

Work in Progress --- Not for Publication 3 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Objectives  Workshop (for each of the nine technologies) –Receive expert inputs (pro & con) –Clarify status, potential, and remaining challenges –Formulate discussion/decision points to be considered in the Wednesday ERD/ERM memory technology assessment meeting  Emerging Research Devices Working Group Mtg. –Discuss and reach approximate consensus on potential & challenges for each technology –Reach approximate consensus on any “New Memory” technologies sufficiently mature to benefit from accelerated development

Work in Progress --- Not for Publication 4 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Evaluation Criteria (Must Have) (1/2)  Potential for scaling beyond the 16nm generation –What is the limit of scaling and limiting factor? –Are there intrinsic statistical fluctuations that could limit scaling*?  How well is the switching physics understood?  CMOS Compatibility? * Large statistical fluctuation in the density of “tokens” for the state –Example: vacancies/cm -3 is ~0.25 vacancies in a cell of a 16nm technology with a 1nm thick active region

Work in Progress --- Not for Publication 5 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Evaluation Criteria (Important) (2/2)  Minimum number of mask layers or photolith steps to fabricate the device? (Cross bar is the minimum).  Means of fabricating a crossbar array and related circuits. –Potential for multiple bits per memory layer –Potential for 3D integration of multiple memory layers  How well are the materials and processes understood?  Operating voltage  Retention time of the state  Amount of energy to change the memory state  Ultimate time constant for changing the state  Number of memory cycles  Parasitic properties that may limit the technology (leakage current, capacitance, etc)  Low sensitivity to environmental performance degradation

Work in Progress --- Not for Publication 6 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Example of Wkshop Deliverable for Each Technology Summary – NEMS Switch (July 12, 2008 Wkshop) Pros  Subthresh slope << 60 mV/dec  Substantial power reduction – lower V dd & little static power  Logic functions ~ 1 delay time  Complementary devices to replace n- and p-MOSFETS  NEM-FET dynamic V th device  Fab process comp w/ CMOS  Low cost substrates  Radiation hard operation Cons  Slow delay time < 1 ns  High oscillatory pull out time  High pull in voltage  Charge based switch w/ parasitics  NEM-FET is still a FET  NEM-FET not demonstrated  Limited scaling potential  Stiction issues  Controlled variability  Hermetic packaging required

Work in Progress --- Not for Publication 7 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Emerging Research Memory Technology Select Mtg. Agenda – Wednesday, April 7, :00Welcome and Introductions Hutchby 9:10Background & ERD Meeting Objectives Hutchby 9:20Review Process for selecting Emerging ResearchHutchby Memory Technologies for Highlighting 9:45Discuss Technologies 9:45Ferroelectric FET MemoryWaser 10:05 Spin Transfer Torque RAMChung 10:25 Nanothermal: NW – PCMChen 10:45Break 11:00 Nanothermal: Fuse/Antifuse MemoryZhirnov 11:20 Nanoionic MemoryAkinaga 11:40 Nanomechanical MemoryZhirnov 12:00 Electronic Effects MemoryZhirnov 12:20Lunch

Work in Progress --- Not for Publication 8 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Emerging Research Memory Technology Select Mtg. Agenda – Wednesday, April 7, :20Lunch 1:20Discuss Technologies 1:20 Macromolecular (polymer) Memory Garner 1:40 Molecular MemoryGarner 2:00Memory Devices: Energy-Space-Time TradeoffsCavin 2:20Execute Memory Technology Selection Process 2:20Preliminary vote on technologies – Majority voting process 2:30Discuss preliminary results 2:50Second vote on technologies 3:00Discuss the leading technologies resulting from vote 3:40Final vote on the 4 – 5 leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and accelerated development 3:50 Decide next steps in roadmapping the chosen technology(ies)

Work in Progress --- Not for Publication 9 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Emerging Research Memory Technology Select Mtg. Agenda – Wednesday, April 7, 2010 (cont’d) 4:10Break 4:30Regular ERD Business Meeting 4:30 ERD Architecture Workshop (August xxx) Cavin 4:45 ERD Device Workshop (Sept. 17) Hutchby 5:00 ERD Analog & RF Workshop (Nov. 30)Brillouet 5:15 ERM Mat’ls for Accelerated Memory (Nov.30)Awano 5:30 Review of ERM Workshops Garner 5:45Adjourn

Work in Progress --- Not for Publication 10 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Process Proposed for Selecting an Emerging Research Memory Technology for Accelerated Development  Receive and evaluate White Papers from Proponents  Conduct an ERD Telecon to briefly review and discuss the White Papers to provide feedback prior to Workshop.  Agree on major technical criteria for each new memory technology  Agree on voting criteria  Receive proponent/opponent expert inputs on the candidate technologies on Tuesday, April 6.  Select any candidate technologies meriting accelerated development via discussion, majority voting, and forming an approximate consensus on Wednesday, April 7.  Report results to IRC on April 8 or 9.  Write a report by May 31.

Work in Progress --- Not for Publication 11 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Decision Making & Majority Voting Scheme  Each member of ERD WG will be given a maximum of 4 votes to use in voting for their top 4 choices among the candidate technologies (Majority Voting scheme)  Only 0 or 1 vote can be cast for any candidate technology  Member does not have to use all 4 votes, but cannot use more than 4 votes.  ERD/ERM WG members and other individuals present in the April 6 th Workshop & the April 7 th FxF meeting will be eligible to participate in the votes in the April 7 th meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation.  The Candidate Technologies will be ordered according to which received the largest number of votes.  Consensus approval will be our goal, but a 75% affirmative vote is desired as a minimum. This is what is meant by the term approximate consensus.

Work in Progress --- Not for Publication 12 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting ERD/ERM Business Meeting April 7, 2010

Work in Progress --- Not for Publication 13 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting 2010 ERD Working Group Organization ERD FunctionLeader u Chapter Chair – North AmericaHutchby u Chapter Co-chair – EuropeIonescu u Chapter Co-chair – Japan ERDHiramoto u Chapter Co-chair – Korea ERDChung u MemoryZhirnov u LogicBourianoff u ArchitectureCavin u Editorial TeamHutchby, Bourianoff, Cavin, Chung, Garner/Herr, Hiramoto, Ionescu, Zhirnov u ITRS Liaisons –PIDSNg, Hutchby –FEPColombo –Modeling & SimulationShankar/Das –MaterialsGarner –MetrologyHerr –DesignYeh/Bourianoff –More than MooreBrillouet

Work in Progress --- Not for Publication 14 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting 2010 ERD Update Schedule  April 6-7 – Memory Workshop  April 7– ERD Business Meeting  April 8 – 9 – ITRS Meetings (no public conference)  June 30? – ERD Presentation draft for July 14 Conf due to Linda Wilson  August xx – Architecture Workshop  July 11 – ERD Business Meeting  July 12 – 13 – ITRS Meetings  July 14 – ITRS Public Conference  Sept. 17– Logic Device Workshop  Sept. 17 – ERD Business Meeting  August ? – ERD Chapter Update Material Due*  Sept. ? – 2008 ITRS Update Content Frozen*  Nov. 30 – 2011 ERD Chapter Kickoff Meeting in Tsukuba, Japan  Dec. 1 – 2 – ITRS Meeting in Tsukuba, Japan  Dec. 3 – ITRS Public Conference in Makuhari Messe, Japan  Dec, 5 – 2011 ERD Chapter Kickoff Meeting in San * ERD typically uses the “update year” to prepare for the following “chapter re-write year (i.e. 2011)” and does not provide an update.

Work in Progress --- Not for Publication 15 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Workshop topicDateLocationMeetingSpecific technology entries Emerging Research Memory Devices April Varese, Italy ITRS Spring meeting Performance analysis for various types of Emerging research memories including: - Spin Transfer Torque MRAM - Nanoionic Memory (e.g. the memrister) -Nanothermal Memory (Nanowire Phase-Change Memory) - Electronics Effects Memory - Molecular Memory Emerging Research Architectures July Semicon West - Performance analysis/benchmarking of various Emerging research information processing device technologies including: - pseudospintronic (e.g., the BiSFET) - Spin devices - Spin wave devices Emerging Research Logic Devices Sept Seville, SpainESSDERC - Nonlinear response functions - Devices for “functional diversification”? - Optimum circuit architectures associated with novel devices 1.RF and Analog Properties of Emerging Research Devices 2.Materials for Select Memories Nov Tokyo, Japan Winter ITRS Mtg To be Determined ERD FxF Workshops for 2010

Work in Progress --- Not for Publication 16 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Action Items (1/2)

Work in Progress --- Not for Publication 17 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting Action Items (2/2)