Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 14, 2013 Energy and Power.

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Presentation transcript:

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 18: October 14, 2013 Energy and Power Basics

Previously Where capacitance arises What drives delay –How to optimize Penn ESE370 Fall DeHon 2

Today Power Sources Static Capacitive Switching Short Circuit (Day 19) Penn ESE370 Fall DeHon 3

Power P=I×V Penn ESE370 Fall DeHon 4

Understanding Currents Penn ESE370 Fall DeHon 5

Operating Modes Steady-State: What modes are the transistors in? –Vin=Vdd –Vin=Gnd What current flows in steady state? Penn ESE370 Fall DeHon 6

Operating Modes Steady-State: Vin=Vdd –PMOS subthreshold –NMOS resistive Penn ESE370 Fall DeHon 7

Static Power Where does I static come from? –Subthreshold leakage –Gate-Drain leakage Penn ESE370 Fall DeHon 8 Vin~=V dd

Data Dependent? How does value of input impact I static ? Penn ESE370 Fall DeHon 9

Data Dependent? How does value of input impact I static ? Penn ESE370 Fall DeHon 10

Static Power P=I×V What V should we use? Penn ESE370 Fall DeHon 11

Power: During Switching P=IV Input switch 1  0 What’s V? What’s I? Where does I go? Penn ESE370 Fall DeHon 12

Power: During Switching P=IV Input switch 1  0 Where does I go? –Vin=Gnd Penn ESE370 Fall DeHon 13

Power: During Switching P=IV Input switch 1  0 Where does I go? –Vin=Gnd Penn ESE370 Fall DeHon 14

Power: During Switching P=IV Input switch 1  0 Where does I go? –Vin=Vdd/2 And Vdd>Vthn+|Vthp| Penn ESE370 Fall DeHon 15

Power: During Switching P=IV Input switch 1  0 Where does I go? –Vin=Vdd/2 And Vdd>Vthn+|Vthp| Penn ESE370 Fall DeHon 16

Switching Currents Charge (discharge) output If both transistor on: –Current path from V dd to Gnd Penn ESE370 Fall DeHon 17

Power: During Switching P=IV Input switch 0  1 What’s V? What’s I? Where does current flow? Penn ESE370 Fall DeHon 18

Power: During Switching P=IV Input switch 0  1 Where does I go? –Vin=Vdd Penn ESE370 Fall DeHon 19

Power: During Switching P=IV Input switch 0  1 Where does I go? –Vin=Vdd Penn ESE370 Fall DeHon 20

Power: During Switching P=IV Input switch 0  1 Where does I go? –Vin=Vdd/2 And Vdd>Vthn+|Vthp| Penn ESE370 Fall DeHon 21

Power: During Switching P=IV Input switch 0  1 Where does I go? –Vin=Vdd/2 And Vdd>Vthn+|Vthp| Penn ESE370 Fall DeHon 22

Observe I changes over time Data dependent At least two components –I static – no switch –I switch – when switch Penn ESE370 Fall DeHon 23

Switching Penn ESE370 Fall DeHon 24

Switching Currents I switch (t) = I sc (t) + I dyn (t) I(t) = I static (t)+I switch (t) Penn ESE370 Fall DeHon 25 I sc I static I dyn

Charging I dyn (t) – why changing? –I ds = f(V ds,V gs ) –and V gs, V ds changing Penn ESE370 Fall DeHon 26

Look at Energy [focus on I dyn (t)] Penn ESE370 Fall DeHon 27

Energy to Switch Penn ESE370 Fall DeHon 28

Integrating Do we know what this is? Penn ESE370 Fall DeHon 29

Capacitor Charge Do we know what this is? What is Q? Penn ESE370 Fall DeHon 30

Capacitor Charge Penn ESE370 Fall DeHon 31

Capacitor Charging Energy Penn ESE370 Fall DeHon 32

Class Ended Here Penn ESE370 Fall DeHon 33

Switching Power Every time output switches 0  1 pay: –E = CV 2 P dyn = (# 0  1 trans) × CV 2 / time # 0  1 trans = ½ # of transitions P dyn = (# trans) × ½CV 2 / time Penn ESE370 Fall DeHon 34

Data Dependent Activity Consider an 8b counter –How often do each of the following switch? Low bit? High bit? –Average switching across all 8 output bits? Assuming random inputs (no glitching) –Activity at output of nand4? –Activity at output of xor4? Penn ESE370 Fall DeHon 35

Glitches Inputs Transition from  –What does output look like? Penn ESE370 Fall DeHon 36

Charging Power P dyn = (# trans) × ½CV 2 / time Often like to think about switching frequency Useful to consider per clock cycle –Frequency f = 1/clock-period P dyn = (#trans/clock) ½CV 2 f Penn ESE370 Fall DeHon 37

Charging Power P dyn = (#trans/clock) ½CV 2 f Let a = activity factor a = average #tran/clock P dyn = a½CV 2 f Penn ESE370 Fall DeHon 38

Chip Level Implications Time Permitting Penn ESE370 Fall DeHon 39

Billion Transistor Leakage 4 Billion transistors Say 1 Billion gates Each with one W=2 transistor leaking How much leakage current? Penn ESE370 Fall DeHon 40

ITRS nm Penn ESE370 Fall DeHon 41 High Performance I sd,leak 100nA/  m I sd,sat 1200  A/  m C g,total 1fF/  m V th 285mV I leak0 =  m × I sd,leak

Leakage Power 4 Billion Transistor chip doing nothing Total Leakage? Leakage Power? Penn ESE370 Fall DeHon 42

Reduce Leakage? P=VI How do we reduce leakage? Penn ESE370 Fall DeHon 43

ITRS nm Penn ESE370 Fall DeHon 44 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV I leak0 =  m × I sd,leak

Low Power Process 4 Billion Transistor chip doing nothing Total Leakage? Leakage Power? Penn ESE370 Fall DeHon 45

ITRS nm Penn ESE370 Fall DeHon 46 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV C 0 =  m × C g,total C 0 = × F

Switching Power 4 Billion Transistors –Organized into 1 billion gates (e.g. nand2) C load = 22C 0 a=0.2 f=1GHz Power? Penn ESE370 Fall DeHon 47

Switching Power V=1V C load =22C 0 ≈ 1 fF = F P=a(0.5× )(N gate )f a=0.2 P= (N gate )f Penn ESE370 Fall DeHon 48

Dynamic vs. Static Power At what speed (f) does leakage power dominate switching power? Penn ESE370 Fall DeHon 49

Compare W N = 2  I leak = 9×10 -9 A P=a(0.5× ) f + 9×10 -9 W a=0.2 P= ×f + 9×10 -9 W For what freqs does leakage power dominate switching power? Penn ESE370 Fall DeHon 50

Ideas Three components of power –Static –Short-circuit –Charging P tot = P static + P sc + P dyn Penn ESE370 Fall DeHon 51

Admin HW6 due Thursday Normal lecture Wednesday and Friday Penn ESE370 Fall DeHon 52