Fixed Abrasive Design for Chemical Mechanical Polishing

Slides:

Advertisements

Similar presentations

Manufacturing, Engineering & Technology, Fifth Edition, by Serope Kalpakjian and Steven R. Schmid. ISBN © 2006 Pearson Education, Inc.,

Advertisements

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process July 30, 2002.

Overview of Nanofabrication Techniques Experimental Methods Club Monday, July 7, 2014 Evan Miyazono.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process.

Pattern transfer by etching or lift-off processes

IC Fabrication and Micromachines

Woodpile Structure Fabrication Chris McGuinness July 8, 2009 Workshop on Novel Concepts for Linear Accelerators and Colliders Working Group 2: Dielectric.

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.

The Deposition Process

YoHan Kim  Thin Film  Layer of material ranging from fractions of nanometer to several micro meters in thickness  Thin Film Process 

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.

Fabrication of Active Matrix (STEM) Detectors

Impact of Nanotopography on STI CMP in Future Technologies D. Boning and B. Lee, MIT N. Poduje, ADE Corp. J. Valley, ADE Phase-Shift W. Baylies, Baytech.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 

8:30 – 9:00Research and Educational Objectives / Spanos 9:00 – 9:45 CMP / Doyle, Dornfeld, Talbot, Spanos 9:45 – 10:30 Plasma & Diffusion / Graves, Lieberman,

Metallization: Contact to devices, interconnections between devices and to external Signal (V or I) intensity and speed (frequency response, delay)

Resistless Fabrication of Embedded Nanochannels by FIB Patterning, Wet Etching and Atomic Layer Deposition Zhongmei Han Marko Vehkamaki Markku Leskelä.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Chapter 2 Manufacturing Process March 7, 2003.

1 K. Overhage, Q. Tao, G. M. Jursich, C. G. Takoudis Advanced Materials Research Laboratory University of Illinois at Chicago.

Chapter Extra-2 Micro-fabrication process

EE235 Presentation I CNT Force Sensor Ting-Ta YEN Feb Y. Takei, K. Matsumoto, I. Shimoyama “Force Sensor Using Carbon Nanotubes Directly Synthesized.

11/8/ Chemical Aspects of CMP SFR Workshop November 8, 2000 Tanuja Gopal and Prof. Jan Talbot UC San Diego La Jolla, CA 2001 GOAL: Build integrated.

Introduction to Wafer fabrication Process

ISAT 436 Micro-/Nanofabrication and Applications

Digital Integrated Circuit Design

PTC Proposal Seongjin Jang September 09, Submit Application To PTC All the users should submit their process-related information to Process Technology.

IC Fabrication Overview Procedure of Silicon Wafer Production

11/8/ Microplasma Optical Emission Spectrometer (MOES) on a chip SFR Workshop November 8, 2000 Michiel Krüger, David Hsu, Scott Eitapence, K. Poolla,

Characterization of Mechanical Properties of Thin Film Using Residual Compressive Stress Sung-Jin Cho, Jin-Won Chung, Myoung-Woon Moon and.

MEMS Micro-Electo-Mechanical Systems By: Kelly Grahmann Meen 3344.

Fabrication of Microelectronic Devices

Digital Integrated Circuits A Design Perspective

Presented by Darsen Lu (3/19/2007)

Chemical Techniques and Developments Mechanical Planarization.

Andrew Chang, David Dornfeld

Fab - Step 1 Take SOI Wafer Top view Side view Si substrate SiO2 – 2 um Si confidential.

SIMULATION OF THE GROWTH OF A HETEROEPITAXIAL FILM ON A (111) ORIENTED SUBSTRATE.

Wafer bonding (Chapter 17) & CMP (Chapter 16)

(Chapters 29 & 30; good to refresh 20 & 21, too)

Micro Electro Mechanical Systems (MEMS) Device Fabrication

1 Device Fabrication And Diffusion Overview 5 and 8 February 2016 Silicon Wafer Production-Refer to Chapter “0” Prologue Raw material ― Polysilicon nuggets.

Solar Cell and NMOS Transistor Process EE290G Joey Greenspun.

Wafer bonding (Chapter 17) & CMP (Chapter 16)

Basic Planar Processes

Layout and fabrication of CMOS circuits

CMOS Process Flow.

Andrew Chang, David Dornfeld

Digital Integrated Circuits A Design Perspective

Silicon Wafer cm (5’’- 8’’) mm

Section 9: CMP EE143 – Ali Javey.

Memscap - A publicly traded MEMS company

Layer Transfer Using Plasma Processing for SMART-Wafer

Enabling Full Profile CMP Metrology and Modeling

MicroElectroMechanical Systems

SILICON MICROMACHINING

Device Fabrication And Diffusion Overview

Silicon Self-Interstitial and Dopant Diffusion

BONDING The construction of any complicated mechanical device requires not only the machining of individual components but also the assembly of components.

K. Takechi and M. A. Lieberman

Acoustic Emission Sensing for Chemical Mechanical Polishing (CMP)

Scratch Testing of Silicon Wafers for Surface Characterization

Jianfeng Luo, Prof. David Dornfeld

IC Fabrication Overview Procedure of Silicon Wafer Production

Jianfeng Luo and David A. Dornfeld

Full Profile CMP Metrology

Jianfeng Luo, David Dornfeld

Device Fabrication And Diffusion Overview

Role of Glycine in Chemical Mechanical Planarization (CMP) of Copper

Presentation transcript:

Fixed Abrasive Design for Chemical Mechanical Polishing SFR Workshop May 24, 2001 Edward Hwang, David Dornfeld Berkeley, CA 2001 GOAL: To build integrated CMP model for basic mechanical and chemical elements. Develop periodic grating metrology by 9/30/2001. 5/24/2001

Content Micro-Fabrication Techniques for Fixed Abrasive for Chemical Mechanical Polishing (CMP) Control of Abrasive Shape Construction of Micro-Scale Wear Mode Diagram 5/24/2001

Background Study & Examples Fixed Abrasive – Cylindrical Shape Pad Conditioner – Random geometry Abrasive shape decides the wear mode 5/24/2001

Standard Fabrication Process Oxide Si Thermal Oxidation Uniform Pattern of Oxide Islands Silicon Etching Silicon Etching Process Determines Abrasive Shape 5/24/2001

Oxidation Sharpening limitations of various abrasive shape with the etching process due to crystallographic structure of silicon Planar Oxidation Non-Planar Oxidation Anomaly of Silicon Oxidation at Regions of High Curvature due to Stress Configuration HF Etching Low Cost 5/24/2001

Simulations with TSUPREM Wet etching + 6 consecutive wet + 4 consecutive dry oxidations at 950 C for 2 ½ hour Dry etching + 6 consecutive dry oxidations at 950 C for 2 ½ hour Isotropic etching + 6 consecutive dry oxidations at 950 C for 2 ½ hour 2-step wet etching + 4 consecutive wet + 4 Consecutive dry oxidations at 950 C for 2 ½ hour 5/24/2001

Scanned Images Dry Etching + Oxidation Wet Etching + Oxidation Oxidation process sharpens the abrasive and sharpened image depends on the precursor 5/24/2001

Lift-Off Technique Additive Process Abrasive Shape deposited material silicon dioxide silicon substrate silicon oxide thickness, the opening 5/24/2001

2002 and 2003 Goals Third axis parameters to be determined Pin-on-disk set-up will be used to complete wear mode diagram Integrate initial chemical models into basic CMP model. Validate predicted pattern development by 9/30/2002. Develop comprehensive chemical and mechanical model. Perform experimental and metrological validation by 9/30/2003. 5/24/2001