Tallinn University of Technology, Department of Computer Engineering, November 2006 Digitaalsüsteemide verifitseerimine Arvutitehnika erikursus II, IAY0110, 2,5 AP, A Jaan Raik IT-208, ,

Tallinn University of Technology, Department of Computer Engineering, November 2006 Digitaalsüsteemide verifitseerimine Õppematerjal: Hardware Design Verification: Simulation and Formal Method-Based Approaches William K. Lam, Sun Microsystems Publisher: Prentice Hall PTR Pub Date: March 03, 2005 ISBN: Pages: 624

Tallinn University of Technology, Department of Computer Engineering, November 2006 Digitaalsüsteemide verifitseerimine 1. Sissejuhatus, verifitseerimise meetodid.( ) 2. Otsustudiagrammid ja ekvivalentsus. (8.1) 3. SAT, sümbolsimuleerimine. ( ) 4. Väited ja SystemVerilog Assertions ( ) 5. Verifitseerimise kattemõõdud (5.6) 6. Mudelikontroll (9) 7. DECIDER: mudelikontroll ja kattegeneraator 8. Verifitseerimine ja HDL (1.6, 2-4)

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER as a model checker

Tallinn University of Technology, Department of Computer Engineering, November 2006 HLDD Coverage Generation

Tallinn University of Technology, Department of Computer Engineering, November 2006 Sequential ATPG No efficient deterministic algorithm known Limited success with simulation-based methods Functional fault models too inaccurate A possible trade-off: hierarchical methods

Tallinn University of Technology, Department of Computer Engineering, November 2006 Hierarchical methods Bottom-up approach (Murray, Hayes ITC’88) –tests generated at the lower level will be later assembled at the higher abstraction level –very fast but… –… incompleteness problem: constraints imposed by other modules may prevent test vectors from being assembled Top-down approach (Lee, Patel TCAD’94) –constraints extracted at the higher level with the goal to be considered when deriving tests for modules at the lower level.

Tallinn University of Technology, Department of Computer Engineering, November 2006 Recent works including DDs Assignment Decision Diagrams + SAT (Ghosh, Fujita DAC’00; Zhang et al. ITC’03) – ADD combined with satisfiability methods High-Level Decision Diagrams (Raik DATE’99) – HLDD based hierarchical ATPG DECIDER – Fault models for FUs and MUXes Shortcomings: – Mainly FUs targeted, control part ignored...

Tallinn University of Technology, Department of Computer Engineering, November 2006 HLDD versus ADD ADDs structure closely matches the RTL design. In HLDDs, a synthesis to extract control relationships has been carried out. ADD model includes four types of nodes (read, write, operator, assignment decision). In HLDD the nodes are treated uniformly. ADDs do not support decision-making implicitly Edges in ADD model have no labels!

Tallinn University of Technology, Department of Computer Engineering, November 2006 High-level decision diagrams Register-Transfer level view of a digital circuit

Tallinn University of Technology, Department of Computer Engineering, November 2006 Decision diagrams for datapath a) Datapath architecture b) Decision diagram

Tallinn University of Technology, Department of Computer Engineering, November 2006 Decision diagrams for control part a) FSM state table b) Decision diagram

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER algorithm General flow

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER algorithm High-level test generation constraints

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER algorithm Fault manifestation (test setup)

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER algorithm Fault effect propagation on HLDDs

Tallinn University of Technology, Department of Computer Engineering, November 2006 Fault effect propagation. Algorithm graph flow

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER algorithm Backtracing (constraint justification)

Tallinn University of Technology, Department of Computer Engineering, November 2006 Backtrace (justification). Algorithm graph flow

Tallinn University of Technology, Department of Computer Engineering, November 2006 Extraction of high-level test constraints

Tallinn University of Technology, Department of Computer Engineering, November 2006 Extraction of high-level test constraints

Tallinn University of Technology, Department of Computer Engineering, November 2006 DECIDER fault models Hierarchical fault model for FUs (Raik DATE’99) Functional fault model for MUX (Raik DDECS’04) Mixed hierarchical-functional fault model for the conditional operators –The main contribution of this paper –Biggest challenge: there is no path through the datapath for observing conditional modules

Tallinn University of Technology, Department of Computer Engineering, November 2006 Fault model for conditions Distinguish correct/faulty values of respective registers Propagate fault effect to an output Justify and apply low-level test patterns

Tallinn University of Technology, Department of Computer Engineering, November 2006 Experimental results

Tallinn University of Technology, Department of Computer Engineering, November 2006 Experimental results

Tallinn University of Technology, Department of Computer Engineering, November 2006 Experimental results

Tallinn University of Technology, Department of Computer Engineering, November 2006 Experimental results

Tallinn University of Technology, Department of Computer Engineering, November 2006 Conclusions and future work A new functional fault model for comparison operators proposed and integrated into the DECIDER system Experiments show that inclusion of the new model increases FC by % Additional fault models needed to fully cover faults in FSMs

Tallinn University of Technology, Department of Computer Engineering, November 2006 VERTIGO plans

Tallinn University of Technology, Department of Computer Engineering, November 2006 Co-operation Run Laerte++ and Decider on same bench- marks and investigate the covered fault sets Pass information from Laerte++ to Decider to target hard faults or check partial solutions To Do: –interface between the engines (var. names etc.) –a proper constraint solver for Decider –support for new fault models