Device Interface Board for Wireless LAN Testing Team May Client ECpE Department Faculty Advisor Dr. Weber Team Members Matthew Dahms – EE Justine Skibbe – EE Joseph Chongo – EE April 26, 2006

Presentation Outline Project Overview  Introduction  Problem Statement  Operating Environment  Intended Users & Uses  Assumptions and Limitations  End-Product Description Project Activities  Previous Accomplishments  Technology Considerations  Present Accomplishments  Planned Activities Resources & Schedule  Estimated Resources  Schedules Closure Materials  Additional Work  Lessons Learned  Risk & Management  Closing Summary Figure 1: Teradyne Lab Entrance

Definitions ASK modulation – Amplitude shift keying. In this modulation scheme the amplitude is varied to indicate logic 0’s and 1’s DUT – Device under test (positive edge D flip-flop) ESD – Electrostatic discharge FPGA – Field programmable gate array. Used to test the DUT after receiving signals from the Teradyne tester Header – Preamble bits sent prior to the sending of information in a data packet time D3 D2 D1 D0 Data Packet Header voltage Figure 2: Data Packet and Header

Definitions (cont.) NRZ – Non-return to zero. Using NRZ, a logic 1 bit is sent as a high value and a logic 0 bit is sent as a low value. PLL – Phase-locked loop RZ – Return to zero. This is the opposite of NRZ data. The signal state is determined by the voltage during the first half of each data binary digit. The signal returns to a resting state (called zero) during the second half of each bit. S/R Network – Send/Receive network. A combination of transmitters and receivers. Teradyne Integra J750 – Tester donated to Iowa State University by Teradyne. It is used in the testing of printed circuit boards and integrated circuits.

Project Overview

Acknowledgement Dr. Weber Nathaniel Gibbs Jason Boyd Rob Stolpman

Project Overview Problem Statement  In Fall 2004, ISU’s ECE Department introduced a senior design project with the goal of developing a wireless interface capable of receiving test signals and transmitting results to the department’s Teradyne Integra J750 tester.  For this project, the goal is to modify the current setup so that the wireless interface shall be capable of recovering a clock signal transmitted by the Teradyne system. Figure 3: Teradyne Integra J750

Project Overview Operating Environment  Operates in a controlled laboratory where the temperature range is 27°C to 33°C  Should be protected from ESD

Project Overview Intended Users  The user has knowledge in electrical and/or computer engineering.  The user has previous experience testing circuits with the Teradyne J750.  The user is familiar with Verilog programming language. Intended Uses  Functional test of a digital device via wireless interface  (Future) Wireless chipset test

Project Overview Assumptions  A sufficient clock-training signal can be sent by the Teradyne J750 over the S/R network to initialize the clock recovering circuitry.  The clock recovering circuit will be able to interact with the existing FPGA.  The current wireless communication network can transmit up to five feet. This assumption is based on the May05 team’s documentation.  The phase difference between the system clock of the Teradyne J750 and the recovered clock at the wireless interface will not be greater than the overall system clock frequency.

Project Overview Limitations  The Teradyne J750 is sensitive to temperature fluctuations and must operate within the calibrated temperature range.  To avoid the loss of data, the maximum rate at which user can send data is at Kbps.  The existing transmitter and receiver communicate at MHz. Therefore, nearby wireless signals at similar frequencies may disrupt the setup.  The communication link shall be limited to one frequency.  Limited to using only one FPGA. Using two FPGA’s, it would be possible to encode/decode the clock and test data into a single data stream. Figure 4: Temperature Requirements

Project Overview End-Product and Other Deliverables  Wireless interface with clock recovering circuit  Demonstration of wireless test  Update the manual for wireless test operation Figure 5: Cover page of wireless manual

Project Activities

Parallel-Serial Conversion  Needed to convert parallel data into serial data for transmission over the S/R network  Chose to use a shift register Figure 6: Shift Register attached to daughterboard Project Activities – Previous

Transmitters and Receivers TRM1 TRM2 RCV1 RCV2 Figure 7: Tx/Rx PCBs Project Activities – Previous

FPGA  Used to recognize header signal  Identifies test data  Presents test data to DUT  Presents reply to S/R network Figure 8: FPGA Project Activities – Previous

Figure 9: Final System Setup

Project Activities – Present Present Accomplishments Hardware Previous team’s project setup and tested PLL tested NRZ/RZ converter tested PCB milled & soldered Software Prototype control software for FPGA written IG-XL test template written

Project Activities – Definition Definition Activities  Initially wanted to test wireless chipset  May 05-29: Redefined project as “proof-of- concept” that J750 can wirelessly test a device  May 06-15: Incorporate clock recovering circuit and the DUT onto a PCB

Project Activities – Research Research Activities  Clock recovery What is it? How to implement it?  Teradyne How do IG-XL templates work? How to send data?

Project Activities – Approach Approach Considered & Used  Technology Considerations Clock recovery  Manchester encoding  PLL & NRZ/RZ converter combination Software  VHDL  Verilog

Project Activities – Approach Original SignalValue Sent Logic 00 to 1 (upward transition at bit centre) Logic 11 to 0 (downward transition at bit centre) The waveform for a Manchester encoded bit stream carrying the sequence of bits Manchester Encoding Figure 11: Graphical representation of Manchester encoding

Manchester Encoding  Advantages Very easy to implement Clock phase and frequency are both present  Disadvantages Too fast for current transmitters and receivers! Project Activities – Approach

PLL & NRZ/RZ converter combination  Advantages Don’t have to build new transmitters and receivers  Disadvantages PLL Must be “trained” Test data must follow a training signal NRZ/RZ converter needed

Project Activities – Approach Figure 10: Phase locked loop transient response a) Output of PLL when locked onto input of PLL b) PLL losing lock when no input is present

Project Activities – Approach Software  VHDL Advantages  Able to handle abstract levels of logic  More powerful than Verilog Disadvantages  This team has no experience using VHDL  Verilog Advantages  More intuitive  Previous team’s code was based on Verilog Disadvantages  No libraries for use in high-level constructs

Project Activities – Approach Hardware chosen - PLL & NRZ/RZ converter combination Language chosen - Verilog

Project Activities – Design Figure 12: Internal Components of a PLL

Project Activities – Design Phase Detector  Type I – XOR  *Type II – Generates lead or lag pulses Voltage Controlled Oscillator (VCO)  Centered at KHz  Frequencies too far off of center frequency will not lock

Project Activities – Design NRZ/RZ Converter: Monostable Multivibrators  Chosen to convert NRZ data to RZ data  Must use an external RC combination to specify pulse widths

Project Activities – Design Figure 14: NRZ to RZ converter circuit with I/O waveforms

Project Activities – Design System Block Diagram Figure 10: Proposed final setup block diagram

Project Activities – Implementation Implementation Activities  Created clock recovering circuit on breadboard  Created PCB layout for final end-product  Created IG-XL test template Completed PCB Breadboard implementation of NRZ/RZ converter, PLL, & DUT

Problems encountered  Pin mapping FPGA grounding problem Errors uploading program to FPGA  Parasitics using breadboard setup Leads on capacitors Crosstalking Project Activities – Implementation

Project Activities – Testing Plan of attack Test components individually w/ function generator & oscilloscope Simulate code Test components individually on breadboard w/ J750 Test PCB components  Test code w/ J750  Test integrated system

Project Activities - Testing FPGA Code Works well in simulation:  Able to recognize header  Able to isolate PLL  Able to send data to DUT  Able to reset for additional sets of test data In practice: Some features of Verilog cannot be implemented by an FPGA. In addition to this, the same register may not be used in multiple “always” block statements.

Resources & Schedule

Schedule  Actual  Original  Revised

Schedule (cont.)  Actual  Original  Revised

Personnel Effort (as of April 26) Personnel Time Commitment *Completed hours ** Left on Co-op PersonnelProblem Definition Technology Considerations and Selection End- Product Design End-Product Prototype Implementation End- Product Testing End-Product Documentation End-Product Demonstration Project Reportin Total Matt Dahms Joe Chongo Srisarath Patneedi * 10*70* Justine Skibbe Total

Previous Team Resources

Financial Resources (w/ labor) ItemW/O LaborWith Labor Parts and Materials: a. Printing of project posterDonated b. Teradyne Integra J750 Test SystemDonated c. Clock Recovery Chips (2)$3.86 d. Dual Monostable Multivib$0.53 e. Supplementary (Res, Cap, etc.) (D)$10.00 f. Voltage Regulators (D)$2.26 g. ZIF w/DIP to SOIC Converter (D)$38.60 h. SOIC CMOS Arrays (2) (D)$1.00 i. SOIC Schmitt Trigger (D)$0.37 j. SOIC PLL (D)$1.93 Labor at $12.00 per hour: a. Matthew Dahms$2,040 b. Joseph Chongo$2.628 c. Srisarath Patneedi$840 d. Justine Skibbe$2,040 Subtotal$7,548 Total$58.55$7,606.55

Closure Materials

Closure Materials – Project Evaluation MilestoneCurrent Progress (%) Scheduled Progress (%) Evaluated Status Evaluation Score (%) WeightTotal Project Definition100 Exceeded Criteria Technology Selection & Usage 100 Exceeded Criteria End-Product Design100 Exceeded Criteria End-Product Implementation 75100Partially Met Criteria End-Product Testing85100Partially Met Criteria End-Product Documentation (Manual) 90100Partially Met Criteria End-Product Demonstration 40100Did Not Meet Criteria Project Reporting (Deliverables) 100 Exceeded Criteria Total10087

Closure Materials - Commercialization Unlikely  Low Speed  Immobile  Inflexible  Cost Inefficient

Closure Materials - Additional Work Consider building faster TX/RX Consider using Manchester encoder/decoder Allow for more advanced DUTs

Closure Materials - Lessons Learned Circuit debugging techniques FPGA implementation Verilog Timing considerations Clock recovery Circuit board layout

Closure Materials - Lessons Learned What went well?  Teamwork  Record keeping  PCB What did not go well?  Damaging parts  Inefficient trouble shooting  FPGA implementations

Closure Materials – Risk Management Risk: Losing Team Member  Management: All members keep detailed & organized notes Risk: Loss of Data  Management: All data will be backed up using team gmail account Risk: Parts Malfunction  Management: Meticulous care in ESD procedures (using ESD bands)

Closing Materials Closing Summary  Problem – Integrate clock recovery circuitry into current system  Solution Use PLL for clock recovery Modify FPGA program to incorporate new components

Questions? Questions???

Thank You