EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Lecturers Dr. Muataz Hameed (RK 53) Dr. Norfadila Mahrom (RK 20) Dr. Rafikha Aliana A. Raof (RK 93)

Schedule / Contact Hours (RK 93) Lectures Tuesday 16:00 – 18:00BPU 5 Friday 09:00 – 10:00 BPU 5 Lab Monday G2: 10:00 – 12:00 MKM7 Thursday G1: 14:00 – 16:00 MKM7

Textbook

Contents (lecture) PART 1: Introduction to Comp. Architecture (Ch. 1) PART 2: Foundation to Comp. Architecture (Ch. 2 & 3) PART 3: Central Processing Unit (CPU) Basics (Ch. 14) PART 4: Processor Internals (Ch. 20 & 21) PART 5: Enhancing CPU Performance (Ch. 16 & 17) PART 6: Computer Memory System (Ch. 4, 5 & 6) PART 7: CPU Externals (Ch. 7) PART 8: RISC (Ch. 15)

VHDL as Hardware Description Language (HDL) Its Coding NOT programming…….Okay? Altera Quartus II as a CAD Tool development platform Laboratory

Course Objectives (CO) Ability to apply the theory and the architecture of a central processing unit (CPU) CO 1 Ability to analyze some of design issues in term of speed, technology, cost and performance. CO 2 Ability to design a simple CPU with applying the theory and knowledge in the lecture. CO 3 Ability to apply appropriate CAD tools to design, verify and test the CPU architecture. CO 4

Coursework (Quiz, Assignment, Mini Project) = 30% Test = 20% Final Exam = 50% Assessment

10 Part I: Introduction to FPGA

11 FPGA evolutionProgrammable logic devicesField programmable gate arraysFPGA design techniquesDesign constraints using FPGAs Why FPGAs?An FPGA Primer

12 1 Higher level of performance 2 level of optimization in the hardware design required 3 Flexible processor option 4 Specific hardware functions and custom hardware design 5 complex controller and specific hardware functions 6 Density 7 Future Modification Why FPGAs?

13 FPGA evolution An FPGA Primer

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15 PAL Programmable logic devices An FPGA Primer 1 Array of logic gates 2 Array of connections 3 Small number of flip-flops (usually <10) 4 Able to implement small state machines

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17 CPLD Programmable logic devices An FPGA Primer 1 Developed to address the limitations of simple PAL devices 2 Same basic principle as PALs 3 Had a series of macro blocks (each roughly equivalent to a PAL) 4 Connected using routing blocks

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19 FPGA An FPGA Primer 1 Dynamic array of gates, the FPGA uses the concept of a Complex Logic Block (CLB) 2 Each logic block can be configured optimally 3 CLB has a Look-Up Table (LUT) that can be configured to give a specific type of logic function 4 A clocked d-type flip-flop that allows the CLB to be combinatorial or synchronous 5 A typical FPGA will have hundreds or thousands of CLBs 6 Modern FPGAs have enough capacity to hold a number of 32-bit processors on a single device

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23 Xilinx

24 Altera

25 Basic FPGA structure

26 Stratix V FPGA Architecture and Features

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28 ALTERA DE2 BOARD

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36 FPGA design techniques An FPGA Primer 1 Mapping: Logic functions mapped onto CLBs 2 Placement: CLBs placed on FPGA 3 Routing: Routed connections between CLBs Connected using routing blocks

37 Design constraints using FPGAs An FPGA Primer FPGAs obviously have a limited number of logic blocks and routing resources, and the designer has to consider this.

38 Current applications 1 Network 2 DSP 3 Parallel processing 4 Hardware emulation 5 Reconfigurable computing 6 Education 7 SoC 8 Embedded system

39 IP 1 Microprocessors 2 Filter 3 Communication elements 4 Arithmetical functions 5 Peripheral controllers 6 DSP functions

40 Digital Devices on the Scale of Programmability and Specialization

41 FPGA Design Steps

ORGANIZATION AND ARCHITECTURE 42

43 Programmer Logical execution of a program Instruction set, number of bits, I/O mechanisms, and techniques for addressing memory…. Computer Architecture Operational units Their interconnections Control signals, interfaces and the memory technology used…. Computer Organization

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