UW-Madison Gate Sizing Based on Lagrangian Relaxation Yu-Min Lee Advisor: Charlie Chung-Ping Chen.

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UW-Madison Gate Sizing Based on Lagrangian Relaxation Yu-Min Lee Advisor: Charlie Chung-Ping Chen

UW-Madison Functionality Gate characterization –Propagation delay –Gate capacitance Posynomial curve fitting Lagrangian relaxation(LR) sizer –Automatic gate sizing –Optimality guarantee for convex programming problem

UW-Madison LR Sizer Structure Gate Lib/ HSPICE Gate Lib/ HSPICE Gate Characterization Gate Characterization LR Sizer Curve Fitting ISCAS Format Circuit ISCAS Format Circuit

UW-Madison Gate Characterization Use HSPICE simulator to characterize the delay of each gate, NOT, NAND, NOR, … with different sizes and load capacitance Use HSPICE simulator to characterize the equivalent input capacitance of each gate, NOT, NAND, NOR, … with different sizes and load capacitance

UW-Madison Curve Fitting: Posynomial Use least-square fitting to find the best posynomial curve for propagation delay, and equivalent capacitance of each gate

UW-Madison LRS (Lagrangian Relaxation Subproblem) The optimal solution for any LRS is a lower bound of the original problem for any type of problem There exists Lagrangian multipliers will lead LRS to find the optimal solution for convex programming problem Lagrangian Relaxation