PS FE Board Tests LHCb - LPC Group R. Bonnefoy, G. Bohner, C. Cârloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq, M-L. Mercier, P. Perret, L. Royer Electronic Calorimeter Final Design Review CERN,

17/02/20052 First tests -- July-September 2004 Testbeam campaign October 2004 « upgraded» prototype -- January 2005 PSFEB Test Bench Conclusion

17/02/20053 Front End Board Synopsis

17/02/20054 Front End Board Synopsis ACQ RAM

17/02/20055 Front End Board first tests Generate & capture all FEB IO’s Fully synchronous ( 1 clock generator) Specially designed: BackPlane (see later) AX1000 with an acquisition RAM LVDS-I2C/LVCMOS-I2C converter Mixed control : LabView (GPIB, VME) C++ (SPECS, USB) I2C/I2C converter

17/02/20056 Wave form generator Clock generator & fan-out Analogue fan-out Digital patterns RAMS Front End Board first tests

17/02/20057 Wave form generator Clock generator & fan-out Analogue fan-out Digital patterns RAMS Front End Board first tests

17/02/20058 Front End Board -- first tests Important software effort in August/September for FEB control/testing and CROC independent data acquisition: Using both SPECS and USB for PGA’s/ASIC’s control Direct reading of the AX1000 Acquisition RAM through I2C/SPECS -> high SPECS error rate! C++ code developped in the VisualC++ environment and running on Windows Specially designed USB/I2C Interface Overcomes SPECS data length limitation (26 bytes/I2C frame, 34 necessary for AX’s & ASICs programation)

17/02/20059 Front End Board --- first tests Important software effort in August/September for FEB control/testing and CROC independent data acquisition: Using both SPECS and USB for PGA’s/ASIC’s control Direct reading of the AX1000 Acquisition RAM through I2C/SPECS -> high SPECS error rate! C++ code developped in the VisualC++ environment and running on Windows Specially designed USB/I2C Interface Overcomes SPECS data length limitation (26 bytes/I2C frame, 34 necessary for AX’s & ASICs programation)

17/02/ Testbeam Campaign 40 MHz pion beam only one channel read out no FE / VFE synchronisation ACQ RAM (trigger controlled, 512 words deep) pedestals OK 10bit/8bit transcoding OK pedestal subtraction OK

17/02/ Test Beam Campaign -- Pedestals 1.2 ADC counts

17/02/ Testbeam Campaign -- Some results ~17 pe, perfectly compatible with previous testbeam results (2002)

17/02/ Single Card PSFEB Testbench Looks pretty much as the automn version except that: now in the LAL backplane DAQ through SEQ_PGA / CROC new SPECS PROM I2C/I2C Converter

17/02/ Control software developped in the CAT (© F Machefert ) framework : multiplatform (soon) integrated control of the analogic (AWG2021) and digital (in developpement) stimuli still necessary to use additional USB layer for PGA’s control It would be nice to have an official decission on the commun calorimeter ECS softw some SPECS improvements (I2C frame length, aknowledge check) Testbench DAQ & Control

17/02/ Single Card Testbench Definition PSVFEB synchronisation resetCheck decoding from TTC channel B clock phaseadjustment of the phase through automatic scan Data processingdigitizationadjustment of the clock phase through automatic scan treatment2 offsets/ 2 gains/ 1 α / 1trigger bit per channel SPD/PS synchronisation data integrity two pipelinescheck pipeline control (delays, bypassing) Data storage and transmission to CROC pipelinecheck behaviour

17/02/ Single Card Testbench Definition Trig_PGAmappingSPD, PS communicationFEB, Validation board algorithmBCId Neighbor searching SEL protectionhardwareSEL simulation with a specially designed board treatmentError bit to be monitored by ECS FE_PGA detection (if applicable) GlobalNoise, stability, crosstalk …

17/02/ Testbench definition Tests of the trigger part FEB Validation Card 1 Validation Card 2 Bottom neighbor top neighbor Right neighbor ECAL1 ECAL2 CROC SPD Multiplicity Left neighbor TTC SPECS L0 SPD

17/02/ Backplane for PSFEB Testbench

17/02/ Testbench definition First bunch of tests for the FEB prototype performed and no serious problem was identified « Almost » ready for the production testing At some point we’ll like to test « real life » communication  –1(2) ECAL cards –1 SPD card –3 PS FEBs –1 Validation Card –1 SPD Multiplicity –32 channels PS FEBs… Conclusion