Calorimeter upgrade meeting - Thursday, 3 April CU (Calorimeter Crate Controller for the Upgrade) Board architecture overview Introduction  Short reminder 3CU (Calorimeter Crate Controller) board architecture  Overview – rear connections with 3U and 6U Backplane – front connections – power supply – main functionalities – GBT link packet format Conclusion

Calorimeter upgrade meeting - Thursday, 3 April 2014 Introduction : short reminder  Calorimeter Crate Controller board Ensure signal distribution inside Front-end crate  Clock distribution from the CROC to all front-end board inside the same crate through backplane  Slow control through 6U backplane  Fast command (BxId Reset, FE Reset, …) through 3U backplane  Crate Power supply  Reused Marathon equipment  Front-end crate with same backplanes and power supply  3U  power supply, clock distribution, …  6U  links between boards inside the same crate  New Front-end board with optical link DAQ and LLT.  New Control Board (3CU)  Remove TVB

3CU Board : Preliminary architecture B25 AB25 B25 AB25 B77 Clock distribution to FEB through 3U_backplane Power Supply: 3V3 / 100A 2V5 / 100A GBLD Edge- connector I2C PCB Laser Diode VTRx TOSA ROSA PD +GBTIA 1 Bi- directionnal link 40MSPS DC-DC Converter 2V5 -> 1V5 Phase ShifterClk Ref / PLL Uplink Down- link E-Port General Ctrl I2C Master …….. Clk Manager Diff. Signal: Clk, D OUT, D IN Buffer PS: 3V3 Ref_Clk[0:7] E-Port_SC_FEB x (16) GBTX E-Port Network Controller User Buses : {I2C, //, SPI, JTAG, 12bADC, …} GBT-SCA Prim. / Second. E-Port_SCA Slow control to FEB DC-DC Converter 2V5 -> 1V2 Protocol used on the board DC-DC Converter 2V5 -> Vcc IO A3PE1500 V CC Core V CC I/O_1 V CC I/O_2 USB SLVS / LVDS Translator Delatching Ctrl. Dedicated Clock IO LVDS Dedicated Clock IO Clock Conditioning Circuit LVDS SLVS / LVDS Translator LVDS Slow Ctrl TTC cmd OnBoard_Clk Crate_Clk Ref_Clk[0] Ext_Clk USB Interface USB Slow Control distribution to FEB through 6U_backplane LEMO In_Ext_Clk Out_Ext_Clk In_2 In_1 Out_2 Out_1 In_Ext_Clk In_1 Out_Ext_Clk Out_2Out_1 In_2 16 FEB Delatching Ctrl line 1V2 tbd Front Rear TTC command In_Ext_Clk E-Port (TTC_cmd) (Clock Conditioning Circuit) Buffer PS: 3V3 TTC command 60x4,6k RAM block 444 Max user I/Os – 8 I/O Banks 6 x CCC TTC cmd distribution to FEB through 3U_backplane

Clock tree  Clock tree of the 3CU board: The clock is provided by the GBTx Chip On the 3CU board we will multiplex the clock with Ext_Clk and On_Board_CLK Ext_Clk (debug) GBTx_Clk On_Board_Clk Crate_Clk Sel  Multiplexing inside A3PE FPGA: For dedicated Clk_IO Clk_IO t PY # 0.9 ns (Pad to data delay through the input buffer with Schmitt trigger disable) Clock Conditioning Circuit (CCC) Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used : # 625 ps  Multiplexing with discret components Necessity to use radhard components  Other solution: Same problem on ATLAS ( see Stefan Simion)  Clock multiplexing several ways possible

3CU Board : rear connection with 3U and 6U Backplane B25 AB25 B25 AB25 B77 Slow control to FEB through 6U backplane (3 differentials pairs between Control slot and each FEB) Delatching control (1point to point connection between each FEB and Control board) Crate Id (8 bit DIP switch on 6U_backplane) Clock distribution from Control board to all slot of the same crate (20 differentials pairs between Control slot and each FEB) Slot ID (4 bit ….) 3V3 / 100A 2V5 / 100A Vfree_1 Vfree_2 Tbd 6U Backplane Connected to 6U backplane 3U Backplane Rear TTC[8:0] Timing Trigger and Control command -5V ?? Current 3U Backplane power supply: 3CU Board Slow control to FEB Buffer PS: 3V3 Crate_Clk Buffer PS: 3V3 TTC command Buffer Current 3U SPECS Bus connection:

3CU Board : front connections GBLD Edge- connector I2C PCB Laser Diode VTRx TOSA ROSA PD +GBTIA 1 Bi- directionnal link 40MSPS GBTX USB Interface USB LEMO In_Ext_Clk Out_Ext_Clk In_2 In_1 Out_2 Out_1 Front Phase ShifterClk Ref / PLL Uplink Down- link E-Port General Ctrl I2C Master …….. Clk Manager Diff. Signal: Clk, D OUT, D IN NIM ?? GBLD GBTIA NC7SZ125 ? Ref_Clk[0:7] In_Ext_Clk ROSA: Receiver Optical Sub Assembly TOSA: Transmitter Optical Sub Assembly

GBT- Power Supply GBLD : Vdd 2V5 GBTIA: Vdd1=2V5 ; Vdd2 =1V5 VTRx power supply: GBTX power supply: 1V5 Digital, Clock manager, Digital IO, phase shifter, receiver, tranceiver E_fuse power 3V3 during programming 1V5 otherwise !! GBT-SCA power supply: 1V2 GBT-SCA footprint: pin CSP BGA (Chip Scale Ball Grid Array) package - Size of the package 10x10mm with a ball pitch of 0.8mm GBTX footprint: - matrix 20x mm pitch - Size 17x17 mm

GBT-link Packet Format  Fixed packet length: 120bits Packet transmission rate: 1/25ns Data transmission rate: 4.8 Gbps  Fixed bandwidth allocation: Trigger path: 640 Mbps Control path: 160 Mbps 1 internal e-link (for GBT management) 1 external e-link (for GBT-SCA chip) Data path: 2.56 Gbps Mbps  Data flow: Transmission of GBT-packets is continuous Data from e-link ports are muxed/demuxed in the GBT-link stream GBT data path is unaware of the e-link transfer protocol.

GBT-link Packet Format Header field (H) : A 4-bit header field is transmitted at the beginning of each frame. Slow Control information (4-bit): Internal Control (IC 2-bit) and External Control (EC 2bit) The 2-bit IC control field is used to control and monitor the GBTX operation. The 2-bit External Control (EC) field has an associated bandwidth of 80 Mb/s and it is part of the slow control channel. Although intended to implement a slow control channel (e.g. for the GBT-SCA) Data field (Data) The 80bit data field is used for generic transmission of data, having an associated bandwidth of 3.2 Gb/s. The data field is fully available to the user via the flexible E-links and is fully protected by the FEC. Forward Error Correction field (FEC) The 32-bit FEC field is used to protect all the other fields in the frame against transmission errors due to link noise and single event upsets. 16-bit TTC command Only 8 decoded on the Control board and transmit to the FEB Mapping of the GBT “frame” on the e-port

Conclusion : Pending questions  Verify the compatibility SLVS LVDS (Tullio Grassi !)  Choice of the Clock multiplexing  Jitter acceptable at the input of the GBTx on the Front-End Board ?  Choice of the FPGA target (A3PE or IGLOO2 ?). The idea is to use the same target of the FEB, if is it possible ?  Disponibility of the GBT_SCA  End of the year (optimistic ! )  Alternative solution, integration of the SCA core in the FPGA  Used of the NIM IN/OUT or other standard (-5V ?)

Calorimeter upgrade meeting - Thursday, 3 April Thank you

Calorimeter upgrade meeting - Thursday, 3 April 2014 SPARES 12

Calorimeter upgrade meeting - Thursday, 3 April 2014 GBT SCA A3PEIGLOO2

Calorimeter upgrade meeting - Thursday, 3 April 2014 GBT SCA A3PE IGLOO2

Calorimeter upgrade meeting - Thursday, 3 April Radiation Hard Optical Link Architecture On-Detector Radiation Hard Electronics Off-Detector Commercial Off-The-Shelf (COTS) GBTX GBTIA GBLD PD LD Custom ASICs Timing & Trigger DAQ Slow Control Timing & Trigger DAQ Slow Control FPGA GBT Versatile Link

Calorimeter upgrade meeting - Thursday, 3 April 2014 The GBT System

Calorimeter upgrade meeting - Thursday, 3 April  ASIC dedicated to slow control functions.  System Upgrades for SLHC detectors.  Replacement for the CCU & DCU ASICs (Communication Control Unit & Detector Control Unit in CMS).  It will implement multiple protocol busses and functions: I2C, JTAG, Single-wire, parallel-port, etc…  It will implement environment monitoring and control functions:  Temperature sensing  Multi-channel ADC  Single channel DAC  Flexible enough to match the needs of different FE systems.  Technology: CMOS 130nm using radiation tolerant techniques. Network Controller Network Controller 16x I2C buses ALARMs e-port JTAG master ADC 8-16 inputs 4x digital I/O Ports 4 DAC RXDATA TXDATA Slow Control e-link SCA Memory Bus (8b) 8 Single Wire bus * * advance information TEM P GBT SCA

Calorimeter upgrade meeting - Thursday, 3 April 2014 SLVS standard SLVS (Scalable Low Voltage Standard) JEDEC standard: JESD8-13 Differential voltage based signaling protocol. Voltage levels compatible with deep submicron processes. Typical link length runs of 30cm over PCB at 1Gbps. Low Power, Low EMI Application in data links for Flat Panel displays in mobile devices. Mobile Pixel Link, MPL-2 (National semi.) 18 SLVS specifications brief 2 mA Differential max Line impedance: 100 Ohm Signal: mV Common mode ref voltage: 0.2V 0.2V 1.2V 400mV 200mV LVDS SLVS