EE210 Digital Electronics Class Lecture 7 May 22, 2008.

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Presentation transcript:

EE210 Digital Electronics Class Lecture 7 May 22, 2008

2 MOS Field-Effect Transistors (MOSFETs)

4.1.7 p-Channel MOSFET (PMOS) Fabricated on n-type substrate with p + regions for D and S and p-channel is induced under gate Operates same way as n- channel device except v GS, V t and v DS are negative Also, i D enters S and leaves D Because NMOS can be made smaller and operate faster and use lower supply voltage than PMOS, it has virtually replaced PMOS

4.1.8 Complementary MOS or CMOS: Complementary MOS or CMOS: In CMOS the NMOS is implemented in p-type substrate and PMOS transistor is formed in a separate n-type region, known as an n well. Separated by thick oxide. Also, as alternate an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

4.2 Current-Voltage Characteristics Circuit Symbol (a) Circuit symbol for the n-channel enhancement- type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant

4.2.2 i D -v DS Characteristics

(a) An n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D – v DS characteristics for a device with k’ n (W/L) = 1.0 mA/V 2.

The i D – v GS characteristic for an enhancement-type NMOS transistor in saturation (V t = 1 V, k’ n W/L = 1.0 mA/V 2 ).

Since the drain current is independent of drain voltage the Saturated MOSFET behaves as an ideal current source whose value is controlled by v GS. Equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

n channel MOSFET p channel MOSFET

4.3 MOSFET Circuits at DC Example 4.2: Design the ckt of Fig so that transistor operates at I D = 0.4mA and V D = +0.5 V. V t = 0.7, u n C ox = 100 uA/V 2, L = 1 um, W=32 um

Mid-Term Exam Friday, June 1, 2007 at 10 am Home Work No. 4 (Due June 2, 2007) Problems at the End Of Chapter 4. 1.Problem Problem Problem Problem 4.113

About Mid-Term Exam … Will Include Following Topics: Representation of Analog Signal by Binary Digital Logic Inverters (General) Propagation Delay and Power Dissipation Diode Logic Gates Propagation Delay BJT as Amp and Switch (VTC) BJT Digital Logic Inverter Saturated vs non-saturated BJT MOSFET Physical Structure and Operation MOSFET as Switch CMOS Digital Logic Inverter and VTC Propagation Delay and Power Dissipation

In Next Class We Will Continue to Discuss: Chap 4 MOS Field-Effect Transistors