1 A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC 班級 : 積體所碩一 學生 : 林義傑 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

2 Outline INTRODUCTION A typical pipeline architecture Amplifier Sharing Technique Power-Reduction Technique Measurement Results Conclusion

3 INTRODUCTION Sharing an amplifier using FSPI technique A wide-swing wide-bandwidth telescopic amplifier an early comparison technique with a constant delay circuit

4 A typical pipeline architecture

5 COMPARISON OF LOW-POWER ARCHITECTURES FOR 10-bit 80-MS/s PIPELINED ADC

6 AMPLIFIER SHARING TECHNIQUE

7 Opamp sharing (FSPI) technique

8 The proposed ADC architecture

9 Scaling of pipeline stages

10 POWER-REDUCTION TECHNIQUES Low-Power High-Bandwidth Opamp Early Comparison Scheme With Constant Delay Circuit Low-Offset Dynamic Comparator

11 Low-power high-bandwidth opamp

12 Constant delay clock generation

13 Die photograph

14 Measured nonlinearity

15 Measured FFT spectrum

16 Dynamic performance versus input frequency

17 Dynamic performance versus duty cycle

18 CONCLUSION The ADC, which occupies 1.85 mm and only consumes 69 mW at 80 MS/s,has been implemented in a 0.18-um DGO CMOS process technology.

19 Reference