Unit - 2 DMA 8237A-5

Basic DMA operation: The direct memory access (DMA) I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. A DMA controller temporarily borrows the address bus, data bus, and control bus from the microprocessor and transfers the data bytes directly between an I/O port and a series of memory locations. The DMA transfer is also used to do high-speed memory-to memory transfers. Two control signals are used to request and acknowledge a DMA transfer in the microprocessor-based system.

DMA Basic DMA operation : The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses after the current bus cycle. The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released control of its buses by placing the buses at their high-impedance states. The HOLD input has a higher priority than the INTR or NMI interrupt inputs.

DMA

DMA Example: memory-to-device transfer

DMA The 8237 DMA controller: The 8237 DMA controller supplies the memory and I/O with control signals and memory address information during the DMA transfer. The 8237 is a four-channel device that is compatible to the 8086/8088 microprocessors and can be expanded to include any number of DMA channel inputs. The 8237 is capable of DMA transfers at rates of up to 1.6M bytes per second. Each channel is capable of addressing a full 64K-byte section of memory and can transfer up to 64K bytes with a single programming.

DMA

DMA Some important signal pins: • DREQ3 – DREQ0 (DMA request): Used to request a DMA transfer for a particular DMA channel. • DACK3 – DACK0 (DMA channel acknowledge): Acknowledges a channel DMA request from a device. • HRQ (Hold request): Requests a DMA transfer. • HLDA (Hold acknowledge) signals the 8237 that the microprocessor has relinquished control of the address, data and control buses.

Some important signal pins: DMA Some important signal pins: • AEN (Address enable): Enables the DMA address latch connected to the 8237 and disable any buffers in the system connected to the microprocessor. (Use to take the control of the address bus from the microprocessor) ADSTB (Address strobe): Functions as ALE to latch address during the DMA transfer. • EOP (End of process): bi direction, Signals the end of the DMA process. • IOR (I/O read): bi-dir, Used as an input strobe to read data from the 8237 during programming and used as an output strobe to read data from the port during a DMA write cycle.

DMA Some important signal pins: IOW (I/O write): bi-dir Used as an input strobe to write data to the 8237 during programming and used as an output strobe to write data to the port during a DMA read cycle. MEMW (Memory write): Used as an output to cause memory to write data during a DMA write cycle. MEMR (Memory read): Used as an output to cause memory to read data during a DMA read cycle A3 – A0 : address pins select an internal register during programming and provide part of the DMA transfer address during DMA operation.

DMA Some important signal pins: A7 – A4 : address pins are outputs that provide part of the DMA transfer address during a DMA operation. DB0 – DB7 : data bus, connected to microprocessor and are used during the programming DMA controller.

DMA Data Transfer modes: Single Transfer Mode In Single Transfer mode the device is programmed to make one transfer only. The word count will be decremented and the address decremented or incremented following each transfer. When the word count ``rolls over'' from zero to FFFFH, a Terminal Count (TC) will cause an Auto initialize if the channel has been programmed to do so.

DMA Block Transfer Mode In Block Transfer mode the device is activated by DREQ to continue making transfers during the service until a TC, caused by word count going to FFFFH, or an external End of Process (EOP) is encountered. DREQ need only be held active until DACK becomes active. Again, an Autoinitialization will occur at the end of the service if the channel has been programmed for it.

DMA Demand Transfer Mode: In Demand Transfer mode the device is programmed to continue making transfers until a TC or external EOP is encountered or until DREQ goes inactive. Transfers may continue until the I/O device has exhausted its data capacity. the DMA service can be re-established by means of a DREQ. During the time between services when the microprocessor is allowed to operate, the intermediate values of address and word count are stored in the 8237A Current Address and Current Word Count registers. EOP can cause an Autoinitialize at the end of the service. EOP is generated either by TC or by an external signal.

DMA Cascade Mode: more than one 8237A together for simple system expansion. The HRQ and HLDA signals from the additional 8237A are connected to the DREQ and DACK signals of a channel of the initial 8237A. This allows the DMA requests of the additional device to propagate through the priority network circuitry of the preceding device.

DMA Software Command: There are 3 software commands used to control the operation of the 8237. These commands do not have a binary bit pattern, A simple output to the correct port number enables the software command. Software commands, Clear the first/last f/f : clear the first/last f/f within the 8237. if F/L = 0, the low order byte is selected for read/write in the current address & current count register. if F/L = 1, the high order byte is selected for read/write in the Master clear : acts same as RESET signal to the 8237, this command disables all channels - Clear mask register : Enables all 4 DMA channels.

8237A – 5 Command & control port assignment DMA 8237A – 5 Command & control port assignment