S YMMETRIC S HARED M EMORY A RCHITECTURE Presented By: Rahul M.Tech CSE, GBPEC Pauri

C ONTENTS Introduction Symmetric memory architecture Advantages The limitations Addressing the limitations Problem with more than one copy in caches Preference for Symmetric in small multiprocessor systems Advantages of meeting bandwidth demand References

S YMMETRIC MEMORY ARCHITECTURE One memory system for the entire multiprocessor system Memory references from all of the processors go to that memory system Shared memory systems can be designed using bus-based or switch-based interconnection networks.

S YMMETRIC MEMORY ARCHITECTURE

S HARED MEMORY SYSTEMS CAN BE DESIGNED USING : Bus Based Symmetric Arch. Switch Based Symmetric Arch.

E XAMPLE OF S YMMETRIC M EMORY A RCHITECTURE *****Uniform Memory Access (UMA)***** Shared memory is accessible by all processors through an interconnection network in the same way a single processor accesses its memory. All processors have equal access time to any memory location.

***G RAPHICAL R EPRESENTATION OF UMA***

A DVANTAGES All of the data in the memory accessible to any processor Never a problem with multiple copies of a given datum existence Tightly Coupled Systems Used for General Purpose and Time Sharing Applications

T HE LIMITATIONS Bandwidth of the Symmetric memory system does not grow as the number of processors in the machine increases Latency of the network added to the latency of each memory reference

A DDRESSING THE LIMITATIONS Many Symmetric-memory multiprocessors provide a local cache for each processor Only send requests that miss in the processor’s cache over the network to the main memory

A DDRESSING THE LIMITATIONS C ONT.. Requests that hit in the cache handled quickly and do not need to travel over the network Reducing the amount of data that the network must carry Thus allowing the main memory to support more processors

P ROBLEM WITH MORE THAN ONE COPY IN CACHES More than one cache may have a copy of a given memory location, creating some cache coherence problem

*****Cache Coherence Problem***** A memory system is coherence, when it satisfies these conditions To the same location, a write immediately followed by a read by the same processor will always return the written value. To the same location, a read from P2 immediately follows a write by P1 will returns the value written by P1 Two writes to the same location by any two processors are seen in the same order by all processors

*** Strategies to maintain coherence in Memory Hierarchy*** Write-Through: The memory is updated every time the cache is updated. Write-Back: The memory is updated only when the block in the cache is being replaced. Write-Invalidate: Maintains consistency by reading from local caches until a write occurs. Write Update: Maintains consistency by immediately updating all copies in all caches.

P REFERENCE FOR S YMMETRIC IN SMALL MULTIPROCESSOR SYSTEMS Symmetric memory systems offer the better design when the number of processors in the system small. For these systems, a single memory system may be able to meet the bandwidth demands of the processors, particularly if each processor has a local cache memory

A DVANTAGES OF MEETING BANDWIDTH DEMAND The reduction in design and programming complexity that comes from not having to manage multiple independent memories

R EFRENCES en.wikipedia.com “Advance Comp. Arch.” by Kai Hwang