in1210/01-PDS 1 TU-Delft The Processing Unit

in1210/01-PDS 2 TU-Delft Problem f y ALU y Decoder a instruction Reg ?

in1210/01-PDS 3 TU-Delft Basic cycle l Assume an instruction occupies a single word in memory l Basic cycle to be implemented: 1. Fetch instruction pointed to by PC and put it in Instruction Register (IR) [IR]  M([PC]) 2.Increment PC: [PC]  [PC] Perform actions as specified in IR

in1210/01-PDS 4 TU-Delft Organization PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU

in1210/01-PDS 5 TU-Delft Register gating RiRi CPU bus Y Z ALU x x x x MUX x Const 4Ri_in Ri_out Y_in Select Z_in Z_out

in1210/01-PDS 6 TU-Delft Operation l Operation cycle includes: -Fetch contents of memory location and put in one of the CPU registers -Store contents of CPU register in memory location -Transfer data from register tot register or to ALU -Perform Arithmetic or Logic operation

in1210/01-PDS 7 TU-Delft Fetch from Memory (1) MDR x Internal processor bus Memory bus Data lines x x x MDR_out MDR_in MDR_outE MDR_inE

in1210/01-PDS 8 TU-Delft Fetch from memory (2) 1. [MAR]  [Ri] 2. Start read on memory bus 3. Wait for MFC response 4.Load MDR from memory bus 5.[Rj]  [MDR] MFC MemoryCPU Read Address Data e.g. LHZ Rj,Ri

in1210/01-PDS 9 TU-Delft Fetch from memory (3) 1.Ri_out, MAR_in, Read 2. MDR_inE, WMFC 3. MDR_out, Rj_in Signal Sequence Activation

in1210/01-PDS 10 TU-Delft Timing of read CLK MAR_in MR 123 address Read MDR_inE Data MFC MDR_out

in1210/01-PDS 11 TU-Delft Store to memory 1. Ri_out, MAR_in 2.Rj_out, MDR_in, Write 3.MDR_outE, WMFC MemoryCPU Write Address Data MFC e.g. STW Rj,Ri

in1210/01-PDS 12 TU-Delft Register Transfers R0 R1 R2 R3 Y Z register file ALU Y_in Z_in Z_outAddress _in R_in R_outCPU bus Address _out F_alu

in1210/01-PDS 13 TU-Delft Copy of registers l Copy contents R1 to R3 1. Address_out = R1 2. R_out 3. Address_in = R3 4. R _ in

in1210/01-PDS 14 TU-Delft Register Transfers R0 R1 R2 R3 Y Z register file ALU Y_in Z_in Z_outAddress _in R_in R_outCPU bus Address _out F_alu

in1210/01-PDS 15 TU-Delft Arithmetic Operation StepAction 1.Address_out  R1 Y_in R_out 2.Address_out  R2 F_alu  “ADD” Z_in  Address_in  R3 Z_out R_in ADD R3,R2,R1

in1210/01-PDS 16 TU-Delft Register Transfers R0 R1 R2 R3 Y Z register file ALU Y_in Z_in Z_outAddress _in R_in R_outCPU bus Address _out F_alu

in1210/01-PDS 17 TU-Delft Arithmetic Operation StepAction 1.Address_out  R1 Y_in R_out 2.Address_out  R2 F_alu  “ADD” Z_in  Address_in  R3 Z_out R_in ADD R3,R2,R1

in1210/01-PDS 18 TU-Delft Register Transfers R0 R1 R2 R3 Y Z register file ALU Y_in Z_in Z_outAddress _in R_in R_outCPU bus Address _out F_alu

in1210/01-PDS 19 TU-Delft Arithmetic Operation StepAction 1.Address_out  R1 Y_in R_out 2.Address_out  R2 F_alu  “ADD” Z_in  Address_in  R3 Z_out R_in ADD R3,R2,R1

in1210/01-PDS 20 TU-Delft Register Transfers R0 R1 R2 R3 Y Z register file ALU Y_in Z_in Z_outAddress _in R_in R_outCPU bus Address _out F_alu

in1210/01-PDS 21 TU-Delft Steps in time Y_in Z_in Z_out R_in 123Step

in1210/01-PDS 22 TU-Delft Register gating 1 bit of common bus line Tri-state based gate C D Q C I R/W R1_out C D Q C I R/W R2_out C D Q C I R/W R3_out

in1210/01-PDS 23 TU-Delft Timing hold time trans- mission time set-up time Rising edge of clock R_ out delay through ALU data available at next register turn output on

in1210/01-PDS 24 TU-Delft Complete instruction 1.Fetch instruction 2. Fetch the operand 3.Perform operation 4.Store result Example ADD (R3),R1 [R1]  M([R3]) + [R1]

in1210/01-PDS 25 TU-Delft Execution fetch(1) StepAction 1PC_out, MAR_in, Read Set carry-in ALU F_alu = “ADD” Z_in  Z_out, PC_in Wait for MFC 3MDR_out, IR_in [PC]  [PC ]+1 [IR]  M([PC ]) Step 1-3: instruction fetch and PC update Note: for architectures having PC:=PC+4 a different scheme must be used

in1210/01-PDS 26 TU-Delft Fetch instruction PC Z ALU PC_in Z_in Z_out ADD MAR PC_out carry MAR_in Read WFMC MDR IR_in MDR_out IR MDR_in

in1210/01-PDS 27 TU-Delft Execution fetch(2) StepAction 1PC_out, MAR_in, Read Set carry-in ALU F_alu = “ADD” Z_in  Z_out, PC_in Wait for MFC 3MDR_out, IR_in Step 1-3: instruction fetch and PC update [PC]  [PC ]+1 [IR]  M([PC ])

in1210/01-PDS 28 TU-Delft Fetch instruction PC Z ALU PC_in Z_in Z_out ADD MAR PC_out carry MAR_in Read WFMC MDR IR_in MDR_out IR MDR_in

in1210/01-PDS 29 TU-Delft Execution fetch(3) StepAction 1PC_out, MAR_in, Read Set carry-in ALU F_alu = “ADD” Z_in  Z_out, PC_in Wait for MFC 3MDR_out, IR_in [PC ]  [PC ]+1 [IR]  M([PC ]) Step 1-3: instruction fetch and PC update

in1210/01-PDS 30 TU-Delft Fetch instruction PC Z ALU PC_in Z_in Z_out ADD MAR PC_out carry MAR_in Read WFMC MDR IR_in MDR_out IR MDR_in

in1210/01-PDS 31 TU-Delft Execute StepAction 4Address_out=R3 MAR_in Read  Address_out=R1, R_out Y_in, Wait for MFC 6MDR_out, Z_in F_alu = “ADD” 7Address_in=R1 Z_out, R_in, End Step 4 and 5: operand fetch Perform addition Store Result

in1210/01-PDS 32 TU-Delft Execute PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU Read

in1210/01-PDS 33 TU-Delft Execute StepAction 4Address_out=R3 MAR_in Read  Address_out=R1, R_out Y_in, Wait for MFC 6MDR_out, Z_in F_alu = “ADD” 7Address_in=R1 Z_out, R_in, End Step 4 and 5: operand fetch Perform addition Store Result

in1210/01-PDS 34 TU-Delft Execute PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU WFMC

in1210/01-PDS 35 TU-Delft Execute StepAction 4Address_out=R3 MAR_in Read  Address_out=R1, R_out Y_in, Wait for MFC 6MDR_out, Z_in F_alu = “ADD” 7Address_in=R1 Z_out, R_in, End Step 4 and 5: operand fetch Perform addition Store Result

in1210/01-PDS 36 TU-Delft Execute PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU

in1210/01-PDS 37 TU-Delft Execute StepAction 4Address_out=R3 MAR_in Read  Address_out=R1, R_out Y_in, Wait for MFC 6MDR_out, Z_in F_alu = “ADD” 7Address_in=R1 Z_out, R_in, End Step 4 and 5: operand fetch Perform addition Store Result

in1210/01-PDS 38 TU-Delft Execute PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU

in1210/01-PDS 39 TU-Delft Branching StepAction 1-3<instruction fetch as in previous example>  PC_out, Y_in 5Off-set-field-IR_out F_alu = “ADD” Z_in 6PC_in Z_out, End

in1210/01-PDS 40 TU-Delft Branching PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU

in1210/01-PDS 41 TU-Delft Branching StepAction 1-3<instruction fetch as in previous example>  PC_out, Y_in 5Off-set-field-IR_out F_alu = “ADD” Z_in 6PC_in Z_out, End

in1210/01-PDS 42 TU-Delft Branching PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU

in1210/01-PDS 43 TU-Delft Branching StepAction 1-3<instruction fetch as in previous example>  PC_out, Y_in 5Off-set-field-IR_out F_alu = “ADD” Z_in 6PC_in Z_out, End

in1210/01-PDS 44 TU-Delft Branching PC CPU bus IR Decoder control R0 R1 R2 R3 register file MAR MDR memory bus Y Z ALU

in1210/01-PDS 45 TU-Delft Conditional branching StepAction 1-3<instruction fetch as in previous example>  PC_out, Y_in If N=0 then End 5Off-set-field-IR_out F_alu = “ADD” Z_in 6PC_in Z_out, End

in1210/01-PDS 46 TU-Delft Control mechanisms l There are two basic control organizations: -Hardwired control -Micro-programmed control

in1210/01-PDS 47 TU-Delft Control Unit Organization Status Flags Condition Codes Control step counter Clock CLK Encoder/ Decoder IR Control signals

in1210/01-PDS 48 TU-Delft Separating decoding/encoding Status Flags Condition Codes End Reset Run Control step counter Clock Step decoder T_1T_n Ins_1 Encoder Instruction decoder IR Ins_n

in1210/01-PDS 49 TU-Delft Generation of control signals ADD T_6T_5 BR T_1 Z_in Z_in = T_1 + T_6. ADD + T_5. BR

in1210/01-PDS 50 TU-Delft End signal End = T_7. ADD + T_6. BR +(T_6. N + T_4. /N). BRN Other example:

in1210/01-PDS 51 TU-Delft PLA’s AND array OR array Control signals IRcounterFlags PLA

in1210/01-PDS 52 TU-Delft Performance l Performance is dependent on: -Power of instructions -Cycle time -Number of cycles per instruction l Performance improvement by: -Multiple datapaths -Instruction prefetching and pipelining -Caches

in1210/01-PDS 53 TU-Delft Multiple datapaths R0 R1 R2 R3 Y register file ALU

in1210/01-PDS 54 TU-Delft Complete CPU Instruction unit Floating-point unit Integer unit Data Cache Instruction Cache Bus Interface Main Memory Input/ Output CPU

in1210/01-PDS 55 TU-Delft Microprogrammed control l All control bits are organized as memory l Each memory location represents a control setting l Memory words are called micro- instructions

in1210/01-PDS 56 TU-Delft Example micro-PC_inMAR_in Addr_inZ_in... instruction

in1210/01-PDS 57 TU-Delft Basic organization IR Starting address generator Clockmicro-PC Control Store Control Signals

in1210/01-PDS 58 TU-Delft Micro-routine AddressMicro-instruction 0PC_out, MAR_in, Read, Set carry-in ALU, F_alu = “ADD”, Z_in  Z_out, PC_in, Wait for MFC 2MDR_out, IR_in 3Branch to starting address routine (here 25) PC_out, Y_in, if N=0 then goto address 0 26Offset-field-of-IR_out, F_alu = “ADD”, Z_in 27Z_out, PC_in, End Fetch Instruction Test N bit New PC address

in1210/01-PDS 59 TU-Delft Detailed organization IR Starting address generator Clockmicro-PC Control Store Control Signals Status flags Control codes

in1210/01-PDS 60 TU-Delft micro-PC l Micro-PC is incremented by 1, except: -At End »Micro-PC is set to first micro-instruction of instruction fetch routine -After loading IR »Micro-PC is set to first micro-instruction for executing machine instruction -At Branch instruction

in1210/01-PDS 61 TU-Delft Why micro-programming l Flexibility -emulation of different instruction sets on same hardware l Support for powerful instructions

in1210/01-PDS 62 TU-Delft Structure micro-instructions l Most simple organization: 1 bit per control signal l However, -Many bits needed (e.g bits) -For many signals only one is needed per cycle; hence they can be grouped -Coding is possible: e.g. an address instead of a single control bit per register

in1210/01-PDS 63 TU-Delft Example Field 1(4 bits):Register address_in Field 2(4 bits):Register address_out Field 3(4 bits):Other registers_in Field 4(4 bits):Function ALU Field 5(2 bit):Read/Write/Nop Field 6(1 bit) :Carry-in ALU Field 7(1 bit) :WMFC Field 8(1 bit) :End F1 F2 F3 F4 F5 F6 F7 F8

in1210/01-PDS 64 TU-Delft Forms of organization l Little coding: horizontal organization -Large words -Little decoding logic -Fast l Much coding: vertical organization -Small control store -Much decoding logic -Slower l Mixed organization

in1210/01-PDS 65 TU-Delft Horizontal/Vertical F0F1F2F3 R0R1R2R3 Horizontal F0F1 Decoder R0R1R2R3 Vertical

in1210/01-PDS 66 TU-Delft Sequencing l Thus far only branch after fetch l No sharing of micro-code between micro- routines l micro-subroutines leads to more efficient control store

in1210/01-PDS 67 TU-Delft Multi-way branching l Number of two-way branches -disadvantage: slows down l More than one branch address in micro- instruction -disadvantage: more bits required l bit-ORing if specified branch address

in1210/01-PDS 68 TU-Delft Example x x x 0 0 x x x x.. micro-instruction Part IR branch address OR actual branch address

in1210/01-PDS 69 TU-Delft Example microroutine(1) ADD (Rsrc)+, Rdst Instruction Format OP code010RsrcRdst Mode IR bit 8: direct/indirect bit 9,10: indexed (11) autodecrement(10) autoincrement(01) register(00)

in1210/01-PDS 70 TU-Delft Example microroutine(2) AddressMicro-instruction 0PC_out, MAR_in, Read, Set carry-in ALU, F_alu = “ADD”, Z_in  Z_out, PC_in, Wait for MFC 2MDR_out, IR_in 3  Branch{  PC  101 (from PLA);  PC_5,4  [IR_10,9];  PC_3  [not.IR_10,].[not.IR_9].[IR_8]} Rsrc_out, MAR_in, Set carry-in ALU,Read, F_alu = “ADD”, Z_in 122Z_out, Rscr_in 123  Branch{  PC  170;  PC_0  [not.IR_8]}, WMFC 170MDR_out, MAR_in, Read, WMFC 171MDR_out, Y_in 172Rdst_out, F_alu = “ADD”, Z_in 173Z_out, Rdst_in, End FETCH

in1210/01-PDS 71 TU-Delft Micro branch address OP code010RsrcRdst Mode IR /IR10./IR9.IR8 PLA

in1210/01-PDS 72 TU-Delft Micro branch address OP code010RsrcRdst Mode IR /IR8 PLA 170

in1210/01-PDS 73 TU-Delft Next address field(1) l Micro-instruction contains address next micro-instruction l Larger store needed l Branch micro-instructions no longer needed

in1210/01-PDS 74 TU-Delft Next-address field(2) IRStatus flags Condition codes Decoding circuits micro-AR Control store Next address Microinstruction decoder micro-IR

in1210/01-PDS 75 TU-Delft Example Field 0(8 bits):Next address Field 1(4 bits):Register address_in Field 2(4 bits):Register address_out Field 3(4 bits):Other registers_in Field 4(4 bits):Function ALU Field 5(2 bit):Read/Write/Nop Field 6(1 bit) :Carry-in ALU Field 7(1 bit) :WMFC Field 8(1 bit) :End PLA/ORing etc F1 F2 F3 F4 F5 F6 F7 F8 F0

in1210/01-PDS 76 TU-Delft Emulation l A micro program determines machine instruction of computer l Suppose we have two computers M1 and M2 with different instruction sets l By adapting the micro-program of M1, we can emulate M2

in1210/01-PDS 77 TU-Delft Organization l Micro-program is often placed in ROM on CPU chip l Some machines had writable control store, i.e. user could change instruction set