Computer Organization and Design Building a Computer! Montek Singh Wed, April 20, 2011 Lecture 15

Building a Computer THIS IS IT! We are now ready to build a computer. The ingredients are all in place, so let’s put them together… I wonder where this goes? ALU A B MIPS Kit Instruction Memory A D 1

Review: The MIPS ISA OP 6 5 16 26 The MIPS instruction set as seen from a Hardware Perspective 000000 rs rt rd func shamt R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] 001XXX rs rt immediate I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) Instruction classes distinguished by types: 3-operand ALU ALU w/immediate Loads/Stores Branches Jumps 10X011 rs rt immediate I-type: Load and Store Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] 10X011 immediate rs rt I-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) 00001X 26-bit constant J-type: jump PC  (PC & 0xf0000000) | 4*(immediate)

Design Approach “Incremental Featurism” We’ll implement circuits for each type of instruction individually, and merge them (using MUXes, etc). Steps: 1. 3-Operand ALU instrs 2. ALU w/immediate instrs 2. Loads & Stores 3. Jumps & Branches 4. Exceptions Our Bag of Components: Registers 1 Muxes ALU A B ALU & adders + Data Memory WD A RD R/W Register File (3-port) RA1 RA2 WA WE RD1 RD2 Instruction D Memories

A Few ALU Tweaks Let’s review the ALU that we built a few lectures ago. (With a few minor additions) A B 5-bit ALUFN Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B X X0 1 1 0 X X1 1 1 1 X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B Add/Sub Bidirectional Barrel Shifter Boolean Sub Bool 0 1 Shft 1 0 Math … 1 0 Flags V,C N Flag R Z Flag

Instruction Fetch/Decode Use a counter to FETCH the next instruction: PROGRAM COUNTER (PC) use PC as memory address add 4 to PC, load new value at end of cycle fetch instruction from memory use some instruction fields directly (register numbers, 16-bit constant) use bits <31:26> and <5:0> to generate controls PC 00 A Instruction 32 Memory +4 D 32 32 INSTRUCTION WORD FIELDS OP[31:26], FUNC[5:0] Control Logic CONTROL SIGNALS

3-Operand ALU Data Path rs rt rd 000000 rs rt rd 100XXX 00000 R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> RA1 Register RA2 Rd: <15:11> WA File WD RD1 RD2 WE WERF 32 32 Control Logic A B ALU ALUFN WERF! ALUFN WERF 32

Shift Instructions rs rt rd 000000 rs rt rd 000XXX shamt R-type: ALU with Register operands sll: Reg[rd]  Reg[rt] (shift) shamt sllv: Reg[rd]  Reg[rt] (shift) Reg[rs] PC 00 Instruction Memory A D +4 Rt: <20:16> Rs: <25:21> RA1 Register RA2 Rd: <15:11> WA File WD RD1 RD2 WE WERF shamt:<10:6> Control Logic 1 ASEL A B ALU ALUFN ASEL! ALUFN WERF ASEL 32

ALU with Immediate rs rt I-type: ALU with constant operand 001XXX rs rt immediate I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> BSEL Rd:<15:11> Rt:<20:16> 1 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 shamt:<10:6> imm: <15:0> SEXT SEXT 1 BSEL Control Logic How do you build SEXT? SEXT A B ALU BSEL! BSEL ALUFN ALUFN WERF ASEL

Load Instruction rs rt 100011 I-type: Load immediate I-type: Load Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> BSEL Rd:<15:11> Rt:<20:16> 1 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 shamt:<10:6> Imm: <15:0> SEXT SEXT Control Logic 1 BSEL SEXT A B BSEL ALU WD R/W Wr ALUFN WDSEL ALUFN Data Memory Wr 32 Adr RD WERF ASEL 32 0 1 2 WDSEL

Store Instruction rs rt I-type: Store 10X011 immediate I-type: Store Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> BSEL Rd:<15:11> Rt:<20:16> 1 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Control Logic 32 No WERF! SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr WERF ASEL WDSEL 0 1 2

PC<31:29>:J<25:0>:00 JMP Instructions PC<31:29>:J<25:0>:00 00001X 26-bit constant J-type: j: PC  (PC & 0xf0000000) | 4*(immediate) jal: PC  (PC & 0xf0000000) | 4*(immediate); Reg[31]  PC + 4 PCSEL 6 5 4 3 2 1 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL J:<25:0> Rd:<15:11> 1 2 Rt:<20:16> RA1 Register RA2 31 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr WERF ASEL PC+4 32 WDSEL 0 1 2

PC<31:29>:J<25:0>:00 BEQ/BNE Instructions PC<31:29>:J<25:0>:00 rs rt BT 10X011 immediate PCSEL 1 2 3 4 5 6 R-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) PC 00 Instruction Memory A D That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions. +4 Rs: <25:21> Rt: <20:16> WASEL Rd:<15:11> Rt:<20:16> 31 J:<25:0> 1 2 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Z x4 Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction. Control Logic + PCSEL WASEL BT SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL 0 1 2

Jump Indirect Instructions PC<31:29>:J<25:0>:00 000000 rs rt rd 00100X 00000 JT BT PCSEL 1 2 3 4 5 6 R-type: Jump Indirect, Jump and Link Indirect jr: PC  Reg[rs] jalr: PC  Reg[rs], Reg[rd]  PC + 4 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL Rd:<15:11> Rt:<20:16> 31 J:<25:0> 1 2 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> JT Z BT + x4 Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL 0 1 2

PC<31:29>:J<25:0>:00 Loose Ends rs rt 001XXX immediate PC<31:29>:J<25:0>:00 JT BT I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 PCSEL 1 2 3 4 5 6 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> Reminder: To evaluate (A < B) we first compute A-B and look at the flags. LT = N  V LTU = C WASEL 31 1 2 J:<25:0> Rd:<15:11> Rt:<20:16> RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Z N JT V C BT + x4 Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr N V C Z WERF ASEL PC+4 32 WDSEL 0 1 2

PC<31:29>:J<25:0>:00 More Loose Ends 000000 rs rt rd 10101X 00000 PC<31:29>:J<25:0>:00 JT BT R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 PCSEL 1 2 3 4 5 6 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL 31 1 2 J:<25:0> Rd:<15:11> Rt:<20:16> RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> JT Z N V C BT + x4 Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr N V C Z WERF ASEL PC+4 32 WDSEL 0 1 2

PC<31:29>:J<25:0>:00 LUI rt PC<31:29>:J<25:0>:00 001XXX 00000 immediate JT BT I-type: Load upper immediate lui: Reg[rt]  Immediate << 16 PCSEL 1 2 3 4 5 6 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL 31 1 2 J:<25:0> Rd:<15:11> Rt:<20:16> RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF Imm: <15:0> SEXT N JT SEXT Z V C BT + x4 shamt:<10:6> Control Logic “16” 1 2 ASEL 1 BSEL PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr N V C Z WERF ASEL PC+4 32 WDSEL 0 1 2

Reset, Interrupts, and Exceptions Upon reset/reboot: Need to set PC to where boot code resides in memory Interrupts/Exceptions: any event that causes interruption in program flow FAULTS: e.g., nonexistent opcode, divide-by-zero TRAPS & system calls: e.g., read-a-character I/O events: e.g., key pressed How to handle? interrupt current running program invoke exception handler return to program to continue execution.

PC<31:29>:J<25:0>:00 Exceptions 0x80000000 0x80000040 PC<31:29>:J<25:0>:00 Reset: PC  0x80000000 0x80000080 JT BT Bad Opcode: Reg[27]  PC+4; PC  0x80000040 PCSEL 1 2 3 4 5 6 IRQ: Reg[27]  PC+4; PC  0x80000080 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL Rd:<15:11> Rt:<20:16> 1 2 3 31 27 J:<25:0> RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF Imm: <15:0> RESET SEXT N JT SEXT IRQ Z V C BT + x4 ASEL 2 shamt:<10:6> “16” 1 Control Logic 1 BSEL PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr N V C Z WERF ASEL LSEL PC+4 32 WDSEL 0 1 2

MIPS: Our Final Version WA PC +4 Instruction Memory A D Register File RA1 RA2 RD1 RD2 ALU B WD WE ALUFN Control Logic Data Memory RD R/W Adr Wr WDSEL 0 1 2 BSEL J:<25:0> PCSEL WERF 00 PC+4 Rt: <20:16> Imm: <15:0> ASEL SEXT Z BT WASEL PC<31:29>:J<25:0>:00 JT N V C Rs: <25:21> 2 1 shamt:<10:6> 3 4 5 6 “16” IRQ 0x80000080 0x80000040 0x80000000 RESET This is a complete 32-bit processor. Although designed in “one” class lecture, it executes the majority of the MIPS R2000 instruction set. Executes one instruction per clock All that’s left is the control logic design WASEL Rd:<15:11> Rt:<20:16> 1 2 3 31 27 BT + x4

MIPS Control The control unit can be built as a large ROM X 1 4 00 6 3 Instruction R E S T I Q Z N V C P L S E X T WA S E L W D S E L ALUFN Sub Bool Shft Math W R W E R F A BS X 1 4 00 6 3 add sll andi lw sw beq