Final Presentation Final Presentation OFDM implementation and performance test Performed by: Tomer Ben Oz Ariel Shleifer Guided by: Mony Orbach Duration: Semester

motivation The TERA-SANTA multiyear project offered a number of projects for students under which the students perform simulations, preliminary tests on a FPGA for future planning. For this there is a need to find pre-planning difficulties on various parts of the system. Therefore, it became necessary to implement an experimental digital receiver according to the initial requirements of the project. Following the implementation of the digital receiver and performance tests you can see where the bottlenecks in the design and suggest ways to improve the speed of the receiver according to the accumulated knowledge in the project.

Project goals Implementation of a digital receiver according to the theory of the OFDM on a FPGA from VIRTEX 5 family. Finding bottlenecks in the planning for future projects. Make a good base for later implementations

Tera-Santa project background Tera-Santa project background The TERA-SANTA project is a joint research between academia and industry. It is funded by magnet program of the State of Israel and managed by Professor Moshe Nazrati. The project's goal is to develop a communication channel to transmit information at a rate of 1]Tbit/s]. The channel will be transferred by optical infrastructure and with the end-station channel will be converted to digital data. The magnitude of the project is enormous and includes many areas in communications, optics, signal processing and more. The Technion research team is responsible for the processing of the digital information channel.

Hardware We used Xilinx’s “xc5vlx 110t-1ff1136“ FPGA device from the Virtex5 family which is place on a ML505 board

The phases of the project 1. Theory 2. Planning 3. Simulation in Simulink 4. Simulations on Chip Scope 5. Bottle necks test

Working environment Simulink via Matlab Xilinx ISE 12.2 Modelsim Xilinx Impact Xilinx ChipScope

Top Level Block diagram

Our actual Top level diagram

DE bouncer DEbouncer – Prevent bouncing of buttons’ signals which are pressed on the board inputs: Reset – Asynchronous reset. D – Trigger from a button on the board. D – Trigger from a button on the board. outputs: Q – The trigger from the button – without bouncing.

FFT Input Vector Block FFT Input Vector - samples to insert to the FFT – to model the ADC output Input: reset – resets the vector Output: Qam4_Out - Vectors to the FFT

FFT Block FFT BLOCK - Calculates FFT of predefined sample width Inputs: xn_re,xn_im– real and imaginary inputs start – start sampling trigger start – start sampling trigger outputs: xk_re,xk_im– real and imaginary outputs

Qam 16 modulation example

Demodulator Block diagram IQ_multi– Shifts the phase of the signal back to its original phase. Inputs: Q in, I in – Current sample’s values; A,B – Correction factors outputs: Q out, I out – The correct signals values. Look Up Table(Qam4) – Translate the signal back to data in bits. Inputs: Q, I – The correct signals values. outputs: QAM4_OUT – The translated data

IQ multiplier Block diagram IQ multiplier– Shifts the phase of the signal back to its original phase.

Simulink simulations per component Simulation on SIMULINK was performed on each component separately to ensure that the required works. For example: The first element we performed tests on was the FFT component – In the initial phase, we put different sequences of vectors using a VHDL written component named “FFT INPUT VECTOR” to the real input of the FFT so that we can process the results and compare to expected values.

Simulink simulations of the system After individual block simulations we simulated the entire system with various input vectors and various error correction values

Matlab vs ChipScope simulations We downloaded the design to the FPGA with a fixed input vector and simulated the design in the Chip Scope and compared those results to Simulink’s results. We encountered minor differences between the two but same general behavior. General behavior is the same Minor changes in values The differences occurred due to CPU calculation differences between the PC and the FPGA.

ISE Timing Analysis Xilinx ‘s ISE reports critical paths and Setup & Hold time constraints These results aren’t suffice for performance analysis but give a good direction for the upcoming performance tests *For example we discovered an inefficient block in our design (Input vectors block)* FFT Block Path Max Frequency

Performance analysis We used a PLL to increase the clock frequency and detect when the design fails After detection of failure we began to analyze the bottle necks

Performance analysis – cont.

Each block’s output was connected to chip scope to better analyze the fails at high frequency FFTFFTQI_MULTQI_MULTDemodulatorDemodulator ChipScopeChipScope

Performance analysis – cont. For example here are the FFT block and the QI_mult blocks outputs QI_mult block’s outputFFT block’s output In this example we see each output’s normal function

Performance analysis – fail example At a high rate (300MHZ) the QI_mult failed first QI_mult block’s outputFFT block’s output Back to the drawing board – enhance the QI_mult block

Performance analysis design iterations example To improve the QI_mult performance we used a different resource – DSP block New DSP for adder Previous ADD/SUB block The DSP block gave much better speed performance that the premade Xilinx’s ADDER

Performance analysis – final results After improving the design as much as we could we reached the final results FFT block’s output The FFT failed at 350MHZ while all other blocks in the design functioned as they should

Final results - Improvement To make the design “lighter” a 16 wide FFT was suggested instead of the heavy 512 width FFT used in the current design 16 wide FFT in 350MHZ16 wide FFT in 380MHZ Although we can see a 30MHZ improvement the FFT continue to stay the design’s bottle neck for speed performance

Summary A design of OFDM receiver has been implemented on FPGA via Simulink-Xilinx interface. After downloading the design to FPGA we have a comparison to the computer simulation We Analyzed the design with Xilinx’s ISE to detect critical paths before starting final performance tests

Summary In the performance tests we detected failures of blocks in the design and improved them to the maximum. After all the enhancements have been placed we came to the conclusion that the FFT is the bottleneck of the design in speed performance.

Summary note The software we used delayed the progress of the project. Xilinx company did not provide good documentation of the components and methods of using them. We asked many members of the Xilinx technical support during the project and found out that they lack courtesy and that their reaction times are long. Therefore, for future projects on the subject we recommend to seek alternative software tools for implementation on a FPGA or alternatively take a wide and comprehensive course on the various Xilinx tools.

Questions?