DAQ Development P. Roger Williamson Hansen Experimental Physics Laboratory Stanford University GLAST Collaboration Meeting GSFC February 10, 1999

prw 2/10/99 DAQ Technical Achievements Stanford HEPL Completed first FPGA/VME board and tested with TKR Delivered VME development subsystem with first FPGA/VME card to UCSC Readout, archive and display TKR data Delivered CAL I/F concept design to NRL Procured PowerPC COTS boards and VME chassis for delivery to subsystem groups VxWorks license in place –SU and NRL have Tornado licenses with WindView and Stethoscope –GSFC and UCSC licensed to use SU and NRL seats –NRL has BSP/driver development kits

prw 2/10/99 DAQ Technical Achievements Stanford HEPL Initial design complete for power conditioning and housekeeping Developed Beam Test Plan 1999 draft document with SLAC Trade studies written to document development of architecture and IDB designs

prw 2/10/99 DAQ Development Plan VME based system for subsystem support and interface development/testing –Subsystem interface cards L1T and TKR Readout tested –COTS CPU for software development, testing, support Utilized MIPS R4700 for initial testing Received three PowerPC COTS boards for subsystem use –Test each TEM subsystem separately L1T TKR Readout in use with TKR at UCSC Continued L1T TKR Readout testing at Stanford Housekeeping and Power Conditioning VME card in work

prw 2/10/99 DAQ Development Plan Utilize minimal interface complexity in Prototype Tower with incremental conversion to flight like –FPGA I/F card supports science subsystem development TKR I/F in use CAL I/F preliminary design delivered ACD I/F preliminary design in work –100 Base T Ethernet for IDB simulation Utilize 10 Base T because of parts limitations on initial TCPU/VME and first TEM board Utilize 100 Base T with COTS TCPU boards

prw 2/10/99 DAQ Development Plan Combine tested interface circuits into a single board for Prototype Tower (begin 1/99) –Cadence parts library 50% complete –Capture TCPU –Combining schematics from FPGA/VME and TCPU/VME Fabricate 4 total TEM boards for DAQ, TKR, CAL, ACD development support and testing prior to integration –Subsystem TEM boards will be dedicated for TKR, CAL, and ACD –Primary data interface between subsystems will be through IDB

prw 2/10/99 Tower Electronics Module (TEM)

prw 2/10/99 DAQ Technical Achievements Overview Current design (Flight) –PowerPC –Switched wormhole router for IDB –LVDS for IDB physical layer –FIFO interface to Main Bus for FPGA readouts –CAL supported by CAL-TEM board –ACD supported by dual, redundant ACD-TEM board

prw 2/10/99 DAQ Technical Achievements Overview Current design (Flight) –CAL supported by CAL-TEM board FPGA readout modified L1T FPGA modified for CAL Power Conditioning CAL specific (includes 40 V PIN supply) CAL-L1T REQ output to TEM board L1T CAL-TEM CPU dedicated to CAL for local processing and sparsify CAL data IDB interface for data transmission to local tower TEM board

prw 2/10/99 DAQ Technical Achievements Overview Current design (Flight) –ACD supported by dual, redundant ACD-TEM board FPGA readout modified L1T FPGA modified for CAL Power Conditioning ACD specific (not including PMT supplies) ACD-L1T outputs to each tower utilize ACD-TEM L1T FPGA ACD-TEM CPU dedicated to ACD for local processing IDB interface for data transmission

prw 2/10/99 Major Milestones ATD start (June 1, 1998) FPGA VME board complete+30 days (11/98) Tracker interface testing9/30/98 Concept review (FSDT) 10/1/98 (1/26/99) Design concept report 12/1/98 (3/22/99?)

prw 2/10/99 Schedule Draft WBS December 1998 Draft management structure December 1998 Draft grassroots cost estimate January 1999 Proposal outline (from Draft AO) February 1999 Update to grassroots cost estimate March 1999 Independent cost study March 1999 Define roles of partners March 1999 Finalize management plan May 1999 Finalize instrument configuration May 1999 First draft of proposal May 1999 Letters of endorsement from sponsoring agencies June 1999 Finalize roles of all partners June 1999 Second draft of proposal June 1999 Internal Red Team review July 1999 External Blue Team review August 1999 Final Proposal Draft August 1999 Proposal production and submission September 1999

prw 2/10/99 DAQ Schedule TCPU Schematic from NRL12/11/98 Second FPGA/VME board test complete12/15/98 TCPU/VME board schematic capture start1/4/99 Housekeeping/power supply VME board3/1/99 TCPU/VME testing start3/1/99 TEM schematic capture complete3/1/99 TEM board submit to fab3/15/99 Beam test interface tests at SLAC6/99 Beam test 1999?/99 CAL-FPGA/VME3/99 ACD-FPGA/VME3/99

prw 2/10/99 Issues and Concerns (June, Sept 1998) Calorimeter interface and sparse readout –Two alternative techniques identified near term –Flight design will be determined by experience with prototype –CAL-TEM used for prototype tower –Re-evaluate interface after prototype tower testing and experience ACD interface –L1T requirement Provision for 12 REQ and 12 REQ in prototype –Tower readout or stand-alone Tower readout for prototype –ACD-TEM resolves multiple tile problems at each tower –Single REQ, single REQBAR from ACD to each tower Instrument Data Bus –Power requirement –Radiation tolerance –100 Base T Ethernet for prototype tower until alternative is ready –Study 2D switched network alternative design

prw 2/10/99 Issues and Concerns (June, Sept 1998) Instrument Data Bus –Power requirement –Radiation tolerance –100 Base T Ethernet for prototype tower until alternative is ready –Study 2D switched network alternative design –No change

prw 2/10/99 Issues and Concerns SSR Trade Study –Working group members selected –Study spacecraft interface to X-band downlink Spacecraft bus selection –1553B or 1773 or ? –IDB to Spacecraft interface for commands and data Programming support –Data flow simulations –Run control web page –glastsim interface for analysis and display of events –Need to reconvene the simulations working group

prw 2/10/99 Issues and Concerns Level 1 Trigger –Have not resolved how to turn off L1T except with fixed dead times Power Margin Inadequate –Power supply efficiency must be included in subsystem allocations (85% max) –Margins must be included in allocation (10% tested parts, 30% design) Proposal concept due by May

prw 2/10/99 Tower CPU VME Board Block Diagram

prw 2/10/99 Tower Electronics Module FIFO PowerPC 603E DMA IDB Node Power Conditioning Housekeeping 64 TKR REQ 2x(16 X,Y) 6 link network TEM Board Tracker ACDVETO ACDREQ SV GPS ADACS +28V (switched ) SV Reset 20 MHz CLK GPS Sync DRAM Level I Trigger Tracker Readout 1773 Data Bus CALREQ 8 TKR I/F Cables EEPROM Level I Trigger PROM