Automated Generation of the Register Set of a SOC and its Verification Environment K. Poulos, K. Adaos, G.P. Alexiou Dept. of Computer Engineering and Informatics Univ. of Patras, Greece 18th Panhellenic Conference on Informatics

Introduction System Environment UVM Register Layer Register Field Template Register File Template Register Generation Procedure Examples Conclusion – Current Work 26-Nov-151Dept. of Computer Engineering and Informatics, Univ. of Patras Agenda

Part of System-on-Chip Platform for Research and Education Result of a graduate thesis in the VLSI Lab of CEID. Target: Develop an automated tool that a)Generates the synthesizabe set of the registers of a SOC b)Generates its verification environment c)Be compliant with design and verification standards Introduction 26-Nov-152Dept. of Computer Engineering and Informatics, Univ. of Patras

System Environment 26-Nov-153Dept. of Computer Engineering and Informatics, Univ. of Patras The register file enables the parts of the system to communicate and control each other.

System Environment 26-Nov-154Dept. of Computer Engineering and Informatics, Univ. of Patras The register file enables the parts of the system to communicate and control each other. – A processor or a HOST system can change the behavior of the SOC

System Environment 26-Nov-155Dept. of Computer Engineering and Informatics, Univ. of Patras The register file enables the parts of the system to communicate and control each other. – A processor or a HOST system can change the behavior of the SOC – Peripherals return data and status

UVM is the industry standard for verification Object Oriented, Based on SystemVerilog Provides a set of predefined agents to control and monitor the bahavior of the DUV Constraint Randomization Techniques UVM Register Layer 26-Nov-156Dept. of Computer Engineering and Informatics, Univ. of Patras

UVM Register Layer is a part of the UVM spec – Models the behavior of the registers of a SOC/HW design based on their properties – Enables frontdoor/backdoor access to the registers during verification – With predefined operations, the user can bypass/omit HW components and focus on the peripheral operation Our tool supports registers named after the UVM register layer => Consistent view of design and verification process. UVM Register Layer 26-Nov-157Dept. of Computer Engineering and Informatics, Univ. of Patras

A generic register template is utilized with an interface that is common in all fields Two access ports: – Bus Port (activated during bus operations) – HW Port (driven by a HW module/state machine). Differentiation is done internally based on the register’s properties Register Field Template 26-Nov-158Dept. of Computer Engineering and Informatics, Univ. of Patras SignalDirectionDescription reset_ninputAsynchronous reset input (active low) clkinputClock input sresetinputSynchronous reset signal (active high) bus_reinputRead enable for the bus bus_weinputWrite enable for the bus bus_dininputData input for the bus hw_weinputWrite enable input for HW blocks hw_dininputData input for the HW blocks qoutputRegister Output bus_doutoutputData output for the bus.

Differentiation is done internally based on the properties of the processor port Register Field Template 26-Nov-159Dept. of Computer Engineering and Informatics, Univ. of Patras Field Typebus we bus din hw we hw din bus re bus dout RO  RW  RC  RS  WRC  WRS  WC   WS   WSRC   WCRS   W1C  W1S  W1T  W0C  W0S  W1SRC  W1CRS  W0SRC  W1CRS  WO  WOC   WOS  

RO : A read only register can be written by HW blocks (via signals hw_we and hw_din) and can only be read by the Bus of the System (via ports bus_re and bus_dout) Register Field Template 26-Nov-1510Dept. of Computer Engineering and Informatics, Univ. of Patras Field Typebus we bus din hw we hw din bus re bus dout RO  RW  RC  RS  WRC  WRS  WC   WS   WSRC   WCRS   W1C  W1S  W1T  W0C  W0S  W1SRC  W1CRS  W0SRC  W1CRS  WO  WOC   WOS  

Register Field Template 26-Nov-1511Dept. of Computer Engineering and Informatics, Univ. of Patras Field Typebus we bus din hw we hw din bus re bus dout RO  RW  RC  RS  WRC  WRS  WC   WS   WSRC   WCRS   W1C  W1S  W1T  W0C  W0S  W1SRC  W1CRS  W0SRC  W1CRS  WO  WOC   WOS   Other register field types model other common HW operations: – W1C: To clear the register, the processor has to write logic-1 (for example for clearing an interrupt flag).

Register Field Template 26-Nov-1512Dept. of Computer Engineering and Informatics, Univ. of Patras Field Typebus we bus din hw we hw din bus re bus dout RO  RW  RC  RS  WRC  WRS  WC   WS   WSRC   WCRS   W1C  W1S  W1T  W0C  W0S  W1SRC  W1CRS  W0SRC  W1CRS  WO  WOC   WOS   RW : A Read/Write field uses all ports

Register Field Code example 26-Nov-1513Dept. of Computer Engineering and Informatics, Univ. of Patras Field Typebus we bus din hw we hw din bus re bus dout RO  RW  RC  RS  WRC  WRS  WC   WS   WSRC   WCRS   W1C  W1S  W1T  W0C  W0S  W1SRC  W1CRS  W0SRC  W1CRS  WO  WOC   WOS  

AHB Register File Architecture 26-Nov-1514Dept. of Computer Engineering and Informatics, Univ. of Patras A register consists of one or more register fields. The AHB bus interface logic adapts the AHB bus signals to the bus access signals (bus_we, bus_re, bus_din, bus_dout). By changing only the bus interface logic we can support bus standards different than the AHB.

Register File Generation 26-Nov-1515Dept. of Computer Engineering and Informatics, Univ. of Patras Generation is based on three input files Register File Desciption (the only file defined by the user) A predesigned Register Field Template A predesigned Register File Template

Register File Generation 26-Nov-1516Dept. of Computer Engineering and Informatics, Univ. of Patras The generator provides three outputs A synthesizable system verilog file with the register file description A C header file (compatible with GNU compilers) The description of the register file according to UVM register layer to be used for verification

Register File Description File 26-Nov-1517Dept. of Computer Engineering and Informatics, Univ. of Patras Name Position - Width Address Type Reset Value Comment (optional)

Register File Description File 26-Nov-1518Dept. of Computer Engineering and Informatics, Univ. of Patras Text Based: Easily Integrates in a Version Control System (we use git) Available parsers can also support spreadsheet files (Microsoft xls or OpenOffice)

Example 26-Nov-1519Dept. of Computer Engineering and Informatics, Univ. of Patras Simple microcontroller (175 total register bits)

Example 26-Nov-1520Dept. of Computer Engineering and Informatics, Univ. of Patras Simple microcontroller (175 total register bits)

Example 26-Nov-1521Dept. of Computer Engineering and Informatics, Univ. of Patras Simple microcontroller (175 total register bits) AreaSpeed TechnologyXilinx Spartan3A UMC 180nXilinx Spartan3A UMC 180n Total Design Area 5,049 LUTs42 K gates50 MHz142 MHz Register File Area 281 LUTs2.72 K gates122 MHz398 MHz

Support of extra register fields and types Support of additional bus standards (Wishbone, APB, AXI) GUI support Extend automation in other SOC components Current Work 26-Nov-1522Dept. of Computer Engineering and Informatics, Univ. of Patras

26-Nov-1523Dept. of Computer Engineering and Informatics, Univ. of Patras Automated Generation of the Register Set of a SOC and its Verification Environment