9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

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Presentation transcript:

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU2 Class 17 – Arithmetic Functions  Iterative Combinational Circuits  Binary Adders  Material from section 4-1 and 4-2 of text

Iterative Circuits  The concept – Create a functional block and create the circuit for doing the multiple bit operation by simply repeating it.  Another concept to be introduced – circuit contraction where you fix the value of some inputs and then can simplify the resulting circuit. Examples are incrementing, decrementing or multiplying by a constant. 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU3

Iterative Circuit  Consider an iterative circuit that operates on two binary vectors.  Base unit  Iterative connection. 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU4

Iterative circuit area  A lot in arithmetic area of application. Adders Subtractors Incrementors Decrementors Multiplication circuits 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU5

Binary Adders  Consider adding 2 binary digits.  Can specify the requirement in a truth table.  A combinational circuit that adds two input bits is called a half adder. 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU6

Half adder equations  The Sum and Carry equations  Implementation 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU7

The full adder  Can evolve half adder into a full adder.  Full adder truth table and minimization. 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU8

The full adder continued  The carry minimization  Implementation 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU9

The full adder  Have just seen a full adder implemented from the structural connection of two half adders and an OR gate.  Can do a direct implementation. It will end up with the same number and type of gates.  For a multibit implementation need a symbol for the unit. 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU10

Multibit use  And then can use that symbol in multibit or hierarchical representations.  A 2 bit example  In this adder the final output carry is generated in the final stage after the carry inputs to all the previous stages has settled. 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU11

Carry ripple  So the carry ripples from the lsb to msb  A ripple carry adder.  All inputs, As,Bs, and C 0 arrive – C 1 becomes valid – C 2 becomes valid – C 3 becomes valid – C 4 becomes valid - 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU12

Class 17 assignment  Covered sections 4-1 through 4-2  Problems for hand in none  Problems for practice 4-2  Reading for next class: sections 4-3, 4-4 9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU13