CSE 291A Interconnection Networks Instructor: Prof. Chung-Kuan, Cheng CSE Dept. UCSD Winter-2007

Course Information  Text books “Principles and Practices of Interconnection Networks” by W. Dally et al. “High Speed Signal Propagation: Advanced Black Magic” by H. Johnson et al. Appendix E of “Interconnection Networks, Computer Architecture: A Quantitative Approach”(4th edition) by Hennessy et al.

Course Information  Grading Help on lecture slides: 15% Projects  Interconnection Network Design: 45%  Subject study: 40% Class participation: 5% bonus

Motivation  Technology advancement: Performance bottleneck shifts from processor to interconnects Optical technology:  In the past: for communication between cities.  Now: for communication between cabinets, or for boards. Distortionless transmission line:  No need for pre-emphasis or equalization.

Motivation (cont’d) New problems:  Moore’s Law: increment of system density and speed.  System integration: array of processors.  Memory wall: maximize bandwidth, minimize latency.  Interface: limit of number of pins.  Power consumption  Communication becomes bottleneck of performance improvements.

Motivation (cont’d)  Applications Distributed computing Internet search engines Computational intensive applications:  Bioengineering: protein and genome  Weather prediction  Image processing  Earthquake simulation

Motivations (cont’d)  Applications Medical applications: MRI, EKG, MKG Synthesis  Systems Supercomputer Internet Router Rapid prototyping

Problem Definition  To link processors, memory banks, disks and I/Os.  Objective function and constraints: Maximize bandwidth Minimize latency Minimize power consumption Volume and cost constraints  Service: Easy to repair Robustness

About volume constraint  For chip, board and mid-plane under given technology: I/O pins and wires have volume. Estimate number of I/O pins and wires.  Design: Interconnection topology Wire technology router

Where is the problem?  Formulation is hard: We need to build a machine for the year We don’t know the state of the art technology at that time.  Complexity: Huge design space Design turnaround Software integration  Physical limit: non-overlapping -> communication latency

Where is the problem (cont’d)  Parallel processing and distributed processing: Competition of resources Delay of feedback