Topics AliasesSubprograms Generics & Configurations

Guangfa Lu March 2003Advanced Topics on VHDL Aliases An alternate name for name items Can significantly improve the readability of VHDL codes by using a shorthand notation for long names. Provides a mechanism to refer to the same named item in different ways.

Guangfa Lu March 2003Advanced Topics on VHDL Aliases signal S: BIT_VECTOR (31 downto 0); Sign Exponent Mantissa OP Reg Base Offset Can represent: Or: An example:

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Syntax: alias identifier [ : identifier-type] is item-name; alias identifier [ : identifier-type] is item-name [signature]; Optional “signature” portion

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Object aliases   Constant   Signal   Variable   File Non-Object aliases   Function names   Literals   Type names   Attribute names Except: labels, loop parameters, and generate parameters

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Examples : constant number_of_bytes : integer :=4; alias N : integer is number_of_byptes; Object aliases:

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Example: Suppose we need to use objects from two different packages, work.alu_types.all and work.io_types.all, and each declare a constant named data_width with different values. Then we have to refer to them as: work.alu_tpes.data_width work.io_types.all.data_width It’s not convenient ! If we include packages as follows: Object aliases:

Guangfa Lu March 2003Advanced Topics on VHDL Aliases We can avoid this by: Introducing two alias declarations into our model! Object aliases:

Guangfa Lu March 2003Advanced Topics on VHDL Aliases None-object aliases: Example: function names literal type name

Guangfa Lu March 2003Advanced Topics on VHDL Aliases With aliases, it is possible to declare something like ‘subtypes’, if the what we required is just a somewhat restricted version of the original type. With aliases, it is possible to declare something like ‘subtypes’, if the what we required is just a somewhat restricted version of the original type. In this way, we break down complex data structures into simpler parts that can be accessed directly. In this way, we break down complex data structures into simpler parts that can be accessed directly.

Guangfa Lu March 2003Advanced Topics on VHDL Aliases An example: function names

Guangfa Lu March 2003Advanced Topics on VHDL Aliases With aliases, it is possible to declare something like ‘subtypes’, if the what we required is just a somewhat restricted version of the original type. With aliases, it is possible to declare something like ‘subtypes’, if the what we required is just a somewhat restricted version of the original type. In this way, we break down complex data structures into simpler parts that can be accessed directly. In this way, we break down complex data structures into simpler parts that can be accessed directly. Notice: we are NOT defining a new data type. However, there are real subtypes.

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Language Features: SUBTYPES SUBTYPE = TYPE + constraints on values   TYPE is the base-type of SUBTYPE   SUBTYPE inherits all the operators of TYPE   SUBTYPE can be more or less used interchangeably with TYPE examples: subtype small_float is real range 0.0 to 1.0;

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Signature alias identifier [ : identifier-type] is item-name [signature]; The “signature” portion is optional. Used for Subprograms Enumeration literals

Guangfa Lu March 2003Advanced Topics on VHDL Aliases Syntax: alias identifier [ : identifier-type] is item-name [signature]; The “signature” portion is optional. [ type_mark,… return type_mark ] Signature’s syntax rule:

Guangfa Lu March 2003Advanced Topics on VHDL Aliases None-object aliases: Example: function names literal type name

Topics AliasesSubprograms Generics & Configurations

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms   Like other programming languages, VHDL provides subprogram facilities in the form of functions and procedures.   VHDL also provided a package facility for collecting declarations and objects into modular units.   Packages also provide a measure of data abstraction and information hiding.

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms Two steps: ① First they must be declared; ② Then they can be called elsewhere.

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms Modes : FunctionsinputProcedures input output Mode:in in out / inout

Guangfa Lu March 2003Advanced Topics on VHDL Functions:  Can be used within an expression;  Can be used to describe frequently used sequential algorithms;  Return a single value;  Execute in zero simulation time (no WAIT allowed). Subprograms : functions

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions Declaration: [pure | impure] function identifier [( parameter_interface_list )] return type_mark is { subprogram_declarative_item } begin { sequential_statements } end [ function ] [ identifier ]; Where parameter_interface_list is: ([ constant | variable | signal ] identifier {, …} : in type_indication [ := static_expression ] ) {,…} mode

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions Example:

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions Declaration: [pure | impure] function identifier [( parameter_interface_list )] return type_mark is { subprogram_declarative_item } begin { sequential_statements } end [ function ] [ identifier ]; Call: identifier [(parameter_association_list )]

Guangfa Lu March 2003Advanced Topics on VHDL Example: Subprograms : functions

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions Declaration: [pure | impure] function identifier [( parameter_interface_list )] return type_mark is { subprogram_declarative_item } begin { sequential_statements } end [ function ] [ identifier ];  By default, functions are declared as pure;  In pure functions, the only accessible data are the input arguments; and the only returned information from this function is the returned value. Pure functions do not have access to objects outside the function.  VHDL’93 introduces impure declaration;  Impure functions must be explicitly declared;  Impure functions can modify data outside their own scope.

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions Example: The file bit_file is an outside object. Since the function is impure, accessing to the file bit_file is possible.

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions Usages of functions:  Returning a value in an expression.  Conversion functions to convert an object of one type to another to convert an object of one type to another  Resolution functions to resolve bus contention on a multiply-driven signal to resolve bus contention on a multiply-driven signal

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions  Conversion functions. are used to convert an object of one type to another to allow mapping of signals and ports of different types. This type of situation usually arises when a designer wants to make use of an entity from anther design that uses a different data type. are used to convert an object of one type to another to allow mapping of signals and ports of different types. This type of situation usually arises when a designer wants to make use of an entity from anther design that uses a different data type.

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : functions  Resolution functions are used to return the value of a signal when the signal is driven by multiple drivers. It is illegal in VHDL to have a signal with multiple drivers without a resolution function attached to it. are used to return the value of a signal when the signal is driven by multiple drivers. It is illegal in VHDL to have a signal with multiple drivers without a resolution function attached to it. A resolution function has a signal-argument input (consists of an unconstrained array of driver values for the signal) and returns a single signal value.

Guangfa Lu March 2003Advanced Topics on VHDL Procedures :  Can be used to partition large behavioral descriptions into modular sections;  A procedure call may be a sequential or concurrent statement;  Arbitrary number of parameters of any possible direction ( in / out / inout );  May or may not execute in zero simulation time. Subprograms : procedures

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Declaration: procedure identifier [( parameter_interface_list )] is { subprogram_declarative_item } begin { sequential_statements } end [ procedure ] [ identifier ]; Where parameter_interface_list is: ([ constant | variable | signal ] identifier {, …} : mode type_indication [ := static_expression ] ) {,…}

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Declaration: procedure identifier [( parameter_interface_list )] is { subprogram_declarative_item } begin { sequential_statements } end [ procedure ] [ identifier ]; Call statement: [ label : ] procedure_name [ (parameter_association_list)];

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Example:

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Default Values in the parameters: When the procedure is called, we can use either leave it out in the caller’s parameter list, or use keyword ‘open’.

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Example: or

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Declaration: procedure identifier [( parameter_interface_list )] is { subprogram_declarative_item } begin { sequential_statements } end [ procedure ] [ identifier ]; Call statement: [ label : ] procedure_name [ (parameter_association_list)]; ;

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures call_proc: p ( s1, s2, val ); call_proc: process is begin p ( s1, s2, val ); wait on s1, s2; end process call_proc; Concurrent Procedure Call Statements: are equivalent to the same procedures with a wait statement, whose sensitivity clause includes the signals mentioned in the parameter list. The equivalent procedure: A concurrent procedure call:

Guangfa Lu March 2003Advanced Topics on VHDL Subprograms : procedures Function: encapsulates a collection of statements that compute a result  generate an expression Procedure: encapsulates a collection of sequential statements to execute  generate a statement

Generics & Configurations

Guangfa Lu March 2003Advanced Topics on VHDL Generics Can we write general models instead of making specific models with VHDL ?

Guangfa Lu March 2003Advanced Topics on VHDL Generics Motivation :  Oftentimes we want to be able to specify a property separately for each instance of a component.  VHDL allows models to be parameterized with generics.  Allows one to make general models instead of making specific models for many different configurations of inputs, outputs, and timing information.  Information passed into a design description from its environment.

Guangfa Lu March 2003Advanced Topics on VHDL Generics A generic entity AND_GATE is generic ( N: natural := 2 ); port ( A: in bit_vector (1 to N ); Z: out bit); end AND_GATE; architecture generic_ex of AND_GATE is begin process (A) variable AND_OUT:bit; begin AND_OUT := ‘1’; for k in 1 to N loop AND_OUT := AND_OUT and A(k); exit when AND_OUT = ‘0’; end loop; Z<=AND_OUT; end process; end GENERIC_EX; AND gate

Guangfa Lu March 2003Advanced Topics on VHDL Generics  A generic declares a constant object of mode in (read only); The value of this constant can be specified as a static expression globally:  Then it can be used in the entity declaration and its corresponding architecture bodies.  The value of a generic must be determined at elaboration time (explicitly specified at least once).

Guangfa Lu March 2003Advanced Topics on VHDL Generics The value for a generic may be specified  in an entity declaration;  in a component declaration;  in a component instantiation.

Guangfa Lu March 2003Advanced Topics on VHDL Generics entity ANOTHER_GEN_EX is end; archiecture GEN_IN_COMP of ANOTHER_GEN_EX is component NAND_GATE generic (M: INTEGER); port (A: in bit_vector(M downto 1); z: out bit); end component; component AND_GATE generic (N: natuaral := 5); port (A: in bit_vector(1 to N); Z: out bit); end component; signal S1, S2, S3, S4: bit; signal SA: bit_vector( 1to 5); signal SB: bit_vector( 2 downto 1); signal SC: bit_vector(1 to 10); signal SD: bit_vector(5 downto 0); begin N1: NAND_GATE generic map (6) port map (SD, S1); --N2: NAND_GATE port map (SB, S2); A1: AND_GATE generic map (N => 10) port map (SC, S3); A2: AND_GATE port map (SA, S4); end GEN_IN_COMP; component declarations component instantiations

Guangfa Lu March 2003Advanced Topics on VHDL Generics Notes:  Generic information is static it can not be changed during the simulation.  Generic value is instance-specific different instances of the same component can have different values.

Guangfa Lu March 2003Advanced Topics on VHDL Configurations  Why we need configurations ? It may be convenient to specify multiple views for a single entity and use any one of them for simulation. For example, there are three architecture bodies, called FA_BEH, FA_STR, and FA_MIXED, corresponding to an entity FULL_ADDER. We can select any of them for simulation by specifying an appropriate configuration.

Guangfa Lu March 2003Advanced Topics on VHDL Configurations  Configurations A VHDL description may consist of many design entities, each with several architectures, and organized into a design hierarchy. The configuration does the job of specifying the exact set of entities and architectures to use, in other words, binding component instances to entities.

Guangfa Lu March 2003Advanced Topics on VHDL Configurations  Configurations Specify which architectures to use for a particular component Specify which architectures to use for a particular component Specify which parameter values to use for a particular component Specify which parameter values to use for a particular component

Guangfa Lu March 2003Advanced Topics on VHDL Configurations  A configuration is therefore used to bind the following pairs: An architecture body to its entity declaration An architecture body to its entity declaration A component with an entity A component with an entity  Definition: Associating an architectural description with a component in a structural model. Associating an architectural description with a component in a structural model.

Guangfa Lu March 2003Advanced Topics on VHDL Configurations  Choose component

Guangfa Lu March 2003Advanced Topics on VHDL Configurations VHDL provides two ways of binding:  By using a configuration specifications Is used to bind component instantiations to specific entities stored in design libraries. Is used to bind component instantiations to specific entities stored in design libraries.  By using a configuration declarations The binding can be performed after the architecture body has been written. The binding can be performed after the architecture body has been written. More than one configuration declaration for an entity is possible. More than one configuration declaration for an entity is possible. The power lies in that the sub-components in an entire hierarchy of a design can be bound using a single configuration declaration. The power lies in that the sub-components in an entire hierarchy of a design can be bound using a single configuration declaration.

Guangfa Lu March 2003Advanced Topics on VHDL Configurations Configuration specifications A VHDL construct which helps associate a particular architecture with an instantiated component … component MYCOMP port ( ….) ; end component ; for U1 : MYCOMP use entity work.MYCOMP(BEHAV); libraryentityarchitecture

Guangfa Lu March 2003Advanced Topics on VHDL Configurations

Guangfa Lu March 2003Advanced Topics on VHDL Configurations

Topics AliasesSubprograms Generics & Configurations