Classification of Simulators Logic Simulators Emulator-basedSchematic-basedHDL-based Event-drivenCycle-basedGateSystem

Classification of Simulators HDL-basedHDL-based: Design and testbench described using HDL –Event-driven –Cycle-based Schematic-basedSchematic-based: Design is entered graphically using a schematic editor EmulatorsEmulators: Design is mapped into FPGA hardware for prototype simulation. Used to perform hardware/software co-simulation.

(Some) EDA Tools and Vendors Logic Simulation –Scirocco (VHDL)  Synopsys –Verilog-XL (Verilog)  Cadence Design Systems –Leapfrog (VHDL)  Cadence Design Systems –VCS (Verilog)  Chronologic (Synopsys) Cycle-based simulation –SpeedSim (VHDL)  Quickturn –PureSpeed (Verilog)  Viewlogic (Synopsys) –Cobra  Cadence Design Systems –Cyclone  Synopsys

Event-driven Simulation Event: change in logic value at a node, at a certain instant of time  (V,T) Event-driven: only considers active nodes –Efficient Performs both timing and functional verification –All nodes are visible –Glitches are detected Most heavily used and well-suited for all types of designs

Event-driven Simulation Event: change in logic value, at a certain instant of time  (V,T) D=2 a b c Events: Input: b(1)=1 Output: none D=2 a b c Events: Input: b(1)=1 Output: c(3)=0 3

Event-driven Simulation Uses a timewheel to manage the relationship between components TimewheelTimewheel = list of all events not processed yet, sorted in time (complete ordering) When event is generated, it is put in the appropriate point in the timewheel to ensure causality

Event-driven Simulation b(1)=1 d(5)=1 D= D=2 a b c d(5)=1 d e c(3)=0 d(5)= e(4)=0 6 e(6)=1

Cycle-based Simulation Take advantage of the fact that most digital designs are largely synchronous Synchronous circuit: state elements change value on active edge of clock Only boundary nodes are evaluated Internal Node Boundary Node LatchesLatches LatchesLatches

Cycle-based Simulation Compute steady-state response of the circuit –at each clock cycle –at each boundary node LatchesLatches LatchesLatches Internal Node

Cycle-based versus Event-driven Cycle-based:Cycle-based: –Only boundary nodes –No delay information Event-driven:Event-driven: –Each internal node –Need scheduling and functions may be evaluated multiple times Cycle-based is 10x-100x faster than event-driven (and less memory usage) Cycle-based does not detect glitches and setup/hold time violations, while event-driven does

Simulation: Perfomance vs Abstraction.001x SPICE Event-driven Simulator Cycle-based Simulator 1x10x Performance and Capacity Abstraction

Simulation Testplan Simulation –Write test vectors –Run simulation –Inspect results About test vectors – HDL code coverage

Digitaalsüsteemide verifitseerimise kursus13 Formal verification Symbolic simulation Can be applied in property checking Or in input space constraining

Digitaalsüsteemide verifitseerimise kursus14 Symbolic simulation Free variables (primary inputs, flip-flops) and internal variables. Considers relations between free variables, not the stimuli values. Good for verifying properties. Circuit unrolling for sequential circuits. Expressions will become complex! BDDS used in representing the expressions.

Digitaalsüsteemide verifitseerimise kursus15 Circuit unrolling: Symbolic simulation

Digitaalsüsteemide verifitseerimise kursus16 Var.1. cycle h gb 1 · c 1 kk1k1 f n j Var.2. cycle h gb 2 · c 2 k f n j Symbolic simulation

Digitaalsüsteemide verifitseerimise kursus17 Symbolic verification Symbolic simulation allows considering several stimuli simultaneously. Thus suitable for verifying properties (assertions) Properties may be time-limited (bound) or time-unlimited (unbound) Symbolic verification can be applied to the former

Digitaalsüsteemide verifitseerimise kursus18 Sisendruumi kitsendamine Mõnedele sisenditele omistatakse konkreetsed väärtused ja simuleeritakse Vähendab oluliselt avaldiste keerukust Eesmärgiks võib olla osalise funktsionaalsuse kontroll (funktsionaalne tükeldamine) või keskkonna kirjeldamine Piiril, kui kõik vabad muutujad omavad väärtust, on tegu traditsioonilise simuleerimisega

Digitaalsüsteemide verifitseerimise kursus19 Sisendruumi kitsendamine sõlm1. takt h gb 1 · c 1 kk1k1 f n j sõlm2. takt h gb 2 · c 2 k f n j

Digitaalsüsteemide verifitseerimise kursus20 Sisendruumi kitsendamine sõlm1. takt h0 gb 1 · c 1 kk 1 k 1 (b 1 · c 1 ) f n j sõlm2. takt h g0 k f n 1 j a 1 =1, c 2 =0

Digitaalsüsteemide verifitseerimise kursus21 Sisendruumi kitsendamine

Digitaalsüsteemide verifitseerimise kursus22 Sisendruumi kitsendamine Olgu sisendid x, y, z ja väljundid p, q x, y, z võivad saada 100, 111, 010, 011 kitsendamiseks kodeerime muutujatega v, w saame x = ¬v, y = v+w, z = w (v, w)(x, y, z)