Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Signal Processing for Nuclear Detectors, Bavarian Forest, 24 April 2009 Dipartimento di Fisica Generale M.P. Bussa, L. Ferrero, A. Grasso, M. Greco, M. Maggiora, Diego ALBERTO

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Outline Introduction Simulated Transmission Chain Simulated WGN Noise SNR and Peak Distortion Simulation Filtering Results Towards FPGA Our Real Transmission Chain Future works

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto The detector detector 1

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Detector The signal generated by the passage of a ionizing particle appeares as a voltage or current pulse This pulse amplitude is proportional to the energy released by the particle inside the detector “Baseline Shift”, “Pulse Pile-Up”, “Ballistic Deficit”, “Noise” During the signal analysis we must pay attention to all those phenomena that can modify time and amplitude measures: Introduction 2

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Simulated Transmission Chain IIR / FIR Noise Filter Simulated Signal i(t) Preamp / Integrator Analog Shaper / Antialias filter PZ comp White Gaussian Noise + ADC sampler quantizer 3

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Noise Causes of noise in an electronic acquisition chain: Thermal noise Thermal noise: is generated by the thermal agitation of the charge carriers inside an electrical conductor and depends on the bandwidth, a larger bandwidth implies a larger noise. Shot noise Shot noise: consists of random fluctuations caused by the fact that the current is carried on by discrete charges that pass through a potential barrier. Flicker noise Flicker noise: low frequency noise, typical on electronic devices, it depends on the generation and recombination processes on the material surface. 4

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Simulation: WGN We started to represent all these kind of noises as an additive White Gaussian Noise (WGN) to the input signal Our aim is the reduction of this noise using digital filters We are now studing other more realistic kinds of noise as the pink one Time [ns] Amplitude Standard vs Adaptive 5

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto SNR and Peak Distortion The Signal to Noise Ratio (SNR) is the ratio between the Signal Power and the Noise Power, usually expressed in dB. In general the power of a digital signal x[n] of N samples is evaluated as: desired filtered With Peak Distortion we intend the relative difference between the desired peak value and the filtered one, it is expressed in percentage Es: Butt. III LP → PD = 8.24 % 6

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Simulation: Standard Butterw III ord. Butterworth III ord. Transfer Function: Infinite Impulse Response ( IIR ) SNR: 5.76 dB PD: 8.24% 7

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto The update coefficients equation Simulation: Adaptive Least Mean Square LMS Adaptive FIR Filter - + best results µ = 0.18 SNR: 6.57 dB PD: 0.06% 8

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Simulation: Butterw vs LMS filtering This analysis has been published on Nuclear Instruments and Methods sect. A 594 (2008), pp DOI information: /j.nima

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Our aim is the implementation of these algorithms on a Xilinx Virtex 4 ML402 FPGA We decided to pass through Simulink and System Generator simulations Towards FPGA 10

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 12 bits 10 bits for the binary point System Generator and ISE (Butt. III LP) FIR section correctly implemented with the HW JTag Cosimulation This retroaction chain could not be automatically implemented with the HW JTag Cos 11

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto VHDL 12 For this reason we started to study VHDL We used Xilinx ISE tool We described in VHDL language some different standard filter structure With ChipeScope we could get the signal filtered by our ML402 Virtex 4 FPGA

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto FPGA elaboration Translating the filter structures into VHDL code written by ourselves we obtained good results with standard filters  # utilized Flip-Flop 315 / ̴ 1%  # 4 inputs LUT 346 / ̴ 1%  # occupied slices 333 / ̴ 2%  max frequency MHz 13

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Analog Chain Qδ(t) Detector i(t) Preamp/ Integr Analog Shaper PZ comp QQQ ADCIIRvsFIR Noise Filter sampler quantizer Digital Chain Q Transmission Chain 14

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Transmission Chain  PC  Xilinx Virtex 4 ML402 FPGA  our analog board  LeCroy 6100A programmable pulse generator Our real transmission chain is composed of a: 15

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Future Works 16 To cope with the implementation of LMS algorithms on FPGA Take into account faster algorithms (as the sign LMS ) To study different and more realistic kinds of noise

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Thank you for the Attention !!

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 20 Simulink Schematics: Butterworth III LP Sys. Gen. Butterworth

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 21 Direct Form II Butt. III LP Butterworth III ord. Transfer Function: Infinite Impulse Response ( IIR )

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 22 System Generator and ISE The filter structure has been synthesized with System Generator (only the Netlist) We had:  to learn VHDL language and Xilinx ISE Tool  to write and manage PIN location, alimentations, filter connections The VHDL code has been included in an ISE project Input ROM Filter Output RAM FPGA Board

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 23 Model Sim code simulation Output Ram

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 24 Simulations comparison Simulating the filtering with Matlab and Model Sim we obtained: Considered the quantization there is a very good matching

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 25 ADC DAC P/Z comp Preampl An. Shaper ADC Filter Test Board Schematics

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 26 PANDA Test Board ORCAD layout Our board

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto 27 First results Input Analog Shaper Output (seen after our DAC, it passed in the FPGA ) Digital Shaper Output Higher Noise in Digital Shaper Output ??