Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory17 October 2001 Delay FPGA I/O Clock40 Reset ADC_Data_stream_0 ADC_Data_stream_3 Delay FPGA delay_ser_out delay_ser_in Configuration JTAG TEMP SENSE - NFBank Drive Voltages Core Voltage, gnd Bank DCI Resistors 10 busy Clock XC2V80FG I/O XC2V40CS I/O Design I/O Total = 73+ ADC_Data_stream_0 ADC_Data_stream_3 5 5 Configuration Bank Ref Voltages 2 Non I/O pins Multi function

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory17 October 2001 Delay FPGA Function REG 10 REG DCM 0 REG SHIFT REG 10 REG DCM 3 IOB REG SHIFT REG 5 Slices 1 4 DPM BLOCK RAM 0 REG IOB DPM BLOCK RAM 3 IOB Counter IOB CONTROL REG CLOCK - 40 MHz RESET Serial In Serial Out busy DATA OUT 0 DATA OUT 3 DCI CLOCK OUT 0 CLOCK OUT 3 2.5/3.3V I/O? 1.5/1.8/2.5/3.3V I/O? Control Clock Counter 10 Slices XC2V40-CS phases

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory17 October 2001 CMS Tracker FED - Front End FPGA Floorplan ADC_Data FE-BE I/O Delay - Opto - ADC XC2V80CS I/O XC2V40CS I/O XC2V250CS I/O Clocks DiePackage Channel 0 Channel 3