Lab. I 1. CADENCE를 이용한 Layout

Physical Design Environment Flow Setup Tech File Developing parameterized cells Defining components Simulating the schematic HSPICE Creating a Schematic Design Entry Laying out and editing designs Virtuoso Layout Editor Generating layout from schematic Connectivity driven layout editing Create abstract cellview Verifying designs LVS, DRC Automatic device level routing Place and Route Parasitic simulation HSPICE Compacting designs and applying design rules Verifying final chip and preparing mask Verifying symbolic designs

Terms and Definitions Library Cell View CIW a collection of cells that corresponds to a specific process technology Cell a design object that forms an individual building block of a chip or system View a defined representation of a cell in the technology file with a registered viewType property CIW the Command Interpreter Window, which is the initial control window that appears when you start Design Framework II

Command Interpreter Window (CIW) Menu banner Log file Input Field SKILL functions or expressions Output Field Running history of commands Invoking Library Manager

Library Structure Library Cell View a collection of cells contains all the different views associated with each of the cells Cell a low-level building block used to create a chip or logical system View a particular representation of a cell each cell can have a layout view, schematic view, symbolic view, and etc.

Library Structure (cont.) sample Cell nmos nmos2 nor2 View symbol layout cdl D G D S S G

Defining Libraries to Edit displays libraries found in the cds.lib file lets you edit the cds.lib online in this form you can add/remove libraries save information to the cds.lib file

Opening a New Library create a new library read a ASCII technology file

Opening a New Design use either the Open File form or the Library Manager

Display Options Display level indicates the highest and lowest levels in the design hierarchy that can be seen in a detailed cellview Grid control minor grid : the distance between each gridpoint major grid : the number of minor gridpoints between each major gridpoint

Layer Selection Window current drawing layer Visibility click with the middle button on the layer name AV : all visible NV : none visible Selectability click with the right button on the layer name AS : all selectable NS : none selectable library name all instances and pins selectable

Selecting Objects Select one object at a time Select all objects in an area click left to select The selected object is highlighted Shift click to select another object drag left mouse

Moving and Stretching Objects Moving objects Stretching objects After selecting an edge the arrow apears Press left on a startpoint Press left on the start point Press and hold the left mouse button until the object is placed. Press and drag the left mouse button to stretch the object

Pan and Zoom Panning let you move your viewing window to different areas of the designs direction : vertical, horizontal, diagonal Zooming let you zoom in or zoom out bindkey : Shift-z(zoom out) Control-z(zoom in) use the arrow keys zoom out [Z] zoom in [^Z]

Bindkey Two command style select object + select command + do command select command + select object + do command When mouse pointer approaches to an objects or an edge, it is highlighted in yellow dashed line When an object is selected, it is highlighted in white line When a command is selected, an instruction appears in the bottom line of the editor window type ‘ESC’ to deselect a command type ‘^D’ to deselect an object

Bindkey (cont) Zoom in z + ‘click SP’ + ‘click EP’ z + ‘drag region’ ruler k + ‘click SP’ + ‘click EP’ K : delete all ruler rectangle r + ‘click SP’ + ‘click EP’ r + ‘drag region’ stretch s + ‘click edge’ + ‘click EP’ Copy c + ‘click object’ + ‘click destination’ delete d + ‘click object’ path p + ‘click SP’ + ‘click MP’ + … + ‘click EP’ full view f : view through the bottom level layout ^F : view only the top level layout *SP : start point *EP : end point *MP : middle point

Layout Example - Inverter 1st version 2nd version

Layout Example - Two Inverters Place two inverters (full view) Place two inverters (top view) align and route

Lab. I 2. CADENCE를 이용한 Circuit Extraction

DIVA Tool DRC (Design Rule Check) Extractor typical checks include material spacing, enclosure, and overlap Extractor device parameters and connectivity are extracted from the layout LVS (Layout Versus Schematic) performs design matching of nets, devices, and device parameters compares any combination of physical or schematic designs

DRC (Design Rule Check) Switch name name parts of the DRC rules you want to execute click left button

Finding Errors with Explain click left button CIW message after DRC finishes

Extraction Extract Method flat : creates a single level extracted view, regardless of the design hierarchy of the layout click left button

Making SPICE Netlist SPICE file name Top Cell Name select top cell name View Name select extracted view Library Name select cell library Output File SPICE file name

Lab. I 3. CADENCE를 이용한 Schematic Edit

Composer Schematic Window Select library name type cell name type ‘schematic’ as view name

Select nmos->symbol Select Component Select nmos->symbol

Select pmos->symbol Place MOS Select pmos->symbol and place PMOS

Connect Wire Add->wire left button click right button click

Add pin 1. Type pin name 2. Click left button

Add VDD/GND Click left button Save schematic Add->component

Create CellView Symbol에서 pin의 위치

Edit Symbol 삼각형은 edit menu 를 이용하여 그린다.

Design Buffer with New Symbol Select new symbol (myinv)

Lab. I 4. CADENCE를 이용한 LVS

LVS(Layout Versus Schematic) Checks the consistency of connectivity and devices between the extracted cellview of a layout and the schematic it was designed from generated from schematic generated from layout

Running LVS and Finding Errors 3 1 2

Analyzing Results Unmatched Pruned Merged net : shows nets that cannot be matched instances : shows device that cannot be matched terminals : shows rewired devices and unmatched pins Pruned net and instances show objects that you want LVS to ignore Merged nets shows nets that, if connected, would compare correctly between views

Lab. I 5. CADENCE를 이용한 16비트 가산기의 설계

실습 과제 - 16비트 가산기 설계 내용 제출 방법 16비트 가산기의 레이아웃 가산기의 종류는 관계없음 셀의 비트당 높이는 60um임 SPICE 시뮬레이션 조건 동작 온도 : 85(centigrade) 입력전압의 rise/fall time : 0.5nsec 출력 load : 0.5pF 사용 공정 0.6um TLM (idec.tf) 제출 방법 homepage에 공지 예정 http://sonata.kaist.ac.kr/course/ideclab

16비트 가산기의 설계 예 (Carry Selector Adder) Sum Generation Logic Sum = A B Ci Carry Cout = A*B + Ci(A + B) Ci Cout A B 1비트 가산기 4비트 가산기

Datapath Design Example Block별로 일정 MUX[0] bit별로 일정 MUX[1] MUX[2] MUX[3] 16-bit adder

Project Directory Setup Setup working directory mkdir ideclab copy environment file idec06.tf (0.6um technology file) display.drf (display resource file) divaDRC.rul (DRC, extraction rule file) divaLVS.rul (LVS rule file) cdsinit (initialization file)

Project를 위한 다음 강의(1/21)의 시간 조정이 있습니다. 조교 연락처 박봉일 : bipark@duo.kaist.ac.kr 양우승 : woosee@duo.kaist.ac.kr 이재곤 : topgon@duo.kaist.ac.kr Project 관련 homepage http://sonata.kaist.ac.kr/course/ideclab Project를 위한 다음 강의(1/21)의 시간 조정이 있습니다. 강의 시간은 1/14일에 정하겠습니다.