Data Acquisition Issues at the International Linear Collider Front End Readout Issues ● Large channel counts require low power consumption power cycling ? ● 1 ms active pipeline for up to 5000 bx local buffering digital or analog ● hit finding, zero suppression on detector itself ACICs on the detector VFE ● high multiplexing to reduce signal cables (material) Gas Amplification R&D Gas Electron Multiplier (GEM)Micro Mesh (MICROMEGAS) TPC R&D Efforts ● ~200 3-dim tracking points ● Low material budget ● Particle ID via dE/dx ● Track reconstruction at large radii ● avoid Ion feedback without gating ● occupancy may be an issue (Aachen, LBNL, Carleton, Montreal, Victoria, DESY, Hamburg, Karlsruhe, Cracow, MIT, MPI Munich, NIKHEF, Novosibirsk, Orsay, Saclay, Rostock) ECAL SiW sampling calorimeter Segmentation: 1cm x 1 cm, 40 layers, 24X 0 ΔE/E =0.11/√E(GeV) ~30Milllion channels HCAL ● Option I: Stainless steel and scintillator tiles with advanced photo detectors ● Option II: Stainless steel and digital readout (RPCs, wire chambers, GEMs) Calorimeter R&D Examples G. Eckerlin (DESY), P. le Du (DAPNIA CEA Saclay), U. Mallik (University of Iowa) and H. Matsunaga (University of Tsukuba) for the DAQ working group of the Worldwide Study of the Physics and Detectors for Future Linear e + e - Colliders The world HEP community has reached consensus that an e + e - Linear Collider with an energy reach of 500GeV to 1TeV should be the next machine to be built and operated before the end of the LHC area. A global R&D and design effort has started aiming for a design report in 2006 of this machine called International Linear Collider. Three detector design studies have so far been launched to elaborate the possible phase space of the detectors to be built. The detector designs are driven by the operational parameters and the physics potentials of this high luminosity machine. The bunched operation of the ILC with a roughly 1ms long pulse train at a rate of 3-5 Hz leading to more than 100ms between trains and very little time between bunches in the train lead to the proposal of a completely trigger less data acquisition system. This 'software trigger' architecture and its consequences to the detector design, the front end electronics and the data acquisition system are presented. Some examples on detector R&D are shown. Today’s ILC Data Collection Network Run Control Monitoring Histograms Event Display DCS Databases... Analysis Farm Mass storage Data logging Config Manager  Local/ worldwide Remote (GDN) Synchronisation NO On line – Off line boundary Local/Global Network(s) Wordlwide! Machine Bx BT feedback Local partition Data collection Sw triggers Sub Detector Read-Out Node (COTS boards) FPGA receiver Buffer FPGA receiver Buffer FPGA receiver Buffer Proc receiver Buffer Data link(s)Services Networking Hub On detector Front End FPGA Possible Common RO Architecture Preamp. Shaper Digitizer VTX CCD MAPS DEPFET ….. TRK Si TPC ECAL SiW Other HCAL Digital Analog Muon RPC Scint VFD & Lumi ….. Detectors technology FPGA Receiver Signal Processing Buffer local data collection node Standard links & protocol USB,Firewire ….. Laptop PC Board Intelligent mezzanine PC… NETWORKNETWORK Ethernet Services Synchro Calibration Monitoring ? Integration to be studied! on detector very FE LOCALBUFFERLOCALBUFFER common/uniform Interface Evolution of DAQ Parameters Sociology Exp. UA’s LEP 3 µsec µsec K Mbit/sec 5-10 MIPS 100 MIPS Collision rate Channel count L1A rate Event building Processing. Power Year LHC ILC 25 ns 330 ns 200 M* 900 M* 100 KHz 3 KHz Gbit/s 10 Gbit/s >10 6 MIPS ~10 5 MIPS ? BaBar Tevatron 4 ns 396 ns 150K ~ 800 K 2 KHz KHz 400 Mbit/s 4-10 Gbit/sec 1000 MIPS MIPS > 2000 ? * including pixels Sub-Detector Pixel Microstrips Fine grain trackers Calorimeters Muon LHC 150 M ~ 10 M ~ 400 K 200 K ~1 M ILC 800 M ~30 M 1,5 M 30 M The vertex detector design : ● 5 layer pixel detector ● Inner Radius: 15mm ● Pixel: 20 x 20 μm 2 ● 800 mio channels ● High occupancy for Layer 1 needs fast readout Vertex Detector R&D Examples Monolithic Active Pixel Sensors Depleted Field Effect Transistor CCD (IReS, LEPSI, RAL, Liverpool, Glasgow, Geneva, NIKHEF) (Bonn, MPI HLL Munich) (LCFI Collaboration: Bristol, Glasgow, Lancaster, Liverpool, Oxford, RAL) Some sensor R&D examples Moderate physics rates e + e - WW → 930 / hour e+e- tt → 70 / hour e+e- HX → 17 / hour top pair production seen by the LDC detector cms energy GeV repetitionrate5 4 Hz bunches/pulse pulse length μs bunch spacing ns luminosity3.4x x10 34 cm -2 s -1 (Parameters are under reconsideration. Values from TESLA TDR are shown)  // 199 ms 1ms 2820 bunches 5 Hz ILC Operation → up to 20kHz bunch crossing rate Detector Concept Studies TPC High granularity calo High precision microvertex 4Tesla LDC GLD SiD Si Strips SiW EM 5 Tesla Large gaseous Tracker (JET or TPC) W/Scint EM cal 3 Tesla Main Tracker EM CalorimeterHad CalorimeterCryostat/Coil Iron Yoke for further information see: ● Worldwide Study of the Physics and Detectors ● SiDhttp://www-sid.slac.stanford.edu ● LDChttp:// ● GLDhttp://ilcphys.kek.jp Readout ASIC on wafer 1-2k channels A Combined ECAL/HCAL prototype is under construction and will be used in test beams. (CALICE Collaboration: 26 Institutes from 9 countries) VME/… HCAL Movable table ECAL Beam monitoring BEAM VME/… HCAL Movable table ECAL Beam monitoring BEAM ASIC multi channel (18) preamp shaping multiplexing low noise low power (5mW/ch) next steps : power cycling ADC integrated dyn. Range >10 4 Event size comparable to ATLAS/CMS LHCb KLOE HERA-B CDF/DO II CDF H1 ZEUS UA1 LEP NA49 ALICE Event Size (bytes) ATLAS CMS Btev Ktev ILC Event Rate