9/25/08J. Lajoie - Muon Trigger Upgrade Review1 Muon Trigger Upgrade LL1 Electronics Iowa State University John Lajoie Cesar Luiz daSilva Todd Kempel Andy Goers Roy McKay Gary Sleege

9/25/08J. Lajoie - Muon Trigger Upgrade Review2 Trigger Algorithm Momentum selectivity through online sagitta measurement –Uses MuTR 1,2,3 and RPC1,3 planes PHENIX LL1 decision time 40xBCLK (4  s) Implement trigger using fast, parallel logic on FPGA’s RPC3 RPC1

9/25/08J. Lajoie - Muon Trigger Upgrade Review3 Trigger Board Block Diagram VME Interface P1 P0 P2 P3 12 x xcvr Virtex-5 LX110T 2.8Gbit) (MuTr 2.8Gbit) (MuTr 2.8Gbit) (MuTr 2.8Gbit) One board processes four trigger octants (one octant per tile). Virtex-5 LX110T (7 fibers per octant) Virtex-5 LX110T Virtex-5 LX110T Virtex-5 LX110T 12 x xcvr 12 x xcvr 12 x xcvr

9/25/08J. Lajoie - Muon Trigger Upgrade Review4 LL1 Trigger Tile Development Rev0 Trigger Tile – Nov’07 –Power supply operation and testing ADuC control, I2C communication –Signal integrity on serial pairs TDR testing to measure pair impedance Rev1 Trigger Tile – April’08 –Full population and assembly –Power consumption FPGA, scaling with GTP use –Testing of FPGA interface JTAG, PROMS, power-up programming –Serial communication testing BERT testing on all serial lines –Chain test with MuTr MRG board Rev2 Trigger Tile – Sept’08 –Minor changes to ease assembly –Revised memory interface and connector More on BERT tests and MRG board tests to follow.

9/25/08J. Lajoie - Muon Trigger Upgrade Review5 The LL1 Trigger Tile

9/25/08J. Lajoie - Muon Trigger Upgrade Review6 Test Stand Setup All GTP Connections Verified –Verified with BERR testing Used Xilinx IBERT tools and GTP internal PRBS generators –All GTP tiles working at 2.8Gbps and 3.125Gbps Using XpressO +/- 50ppm clock BERR < 5.1x with 8b/10b –Tested up to 8 tiles (16 GTP’s) in single LX110T design Requires heat sink and fan Current draw as expected (~2A on 3.3V w/all GTP’s)

9/25/08J. Lajoie - Muon Trigger Upgrade Review7 MuTr MRG to LL1 Data Format TLK3101 (TI) TLK3101 (TI) 140MHz data[15:0] TX_EN TX_ER FTLF8524E2KNL (finisar) FTLF8524E2KNL (finisar) Optical driver 850nm laser ….…… Header Carrier Extend(no data) idle to LL1 event data 14 packets for 1 cycle additional idle packet owing to asynchronous system (9.4x14MHz  140MHz) next event color Data format agreed to between LL1 and MuTr FEE group (April ’08 workshop at ISU).

9/25/08J. Lajoie - Muon Trigger Upgrade Review8 Communication Tests Two MRG Board Prototypes Pattern Generator for input LL1 Trigger Tile Laptop for power control, chip monitoring (voltages, temps, etc), Chipscope for signal monitoring ~30m fiber connecting the two boards

9/25/08J. Lajoie - Muon Trigger Upgrade Review9 MRG->LL1 Testing at BNL (Aug ’08) Optical connection between MRG and LL1 trigger tile established: –Patterns sent from MRG board with alternating parity –Parity calculated and checked at LL1 end –System ran for ~14 hrs w/o error –Clock domain logic in tile FPGA fully tested (REF, 14xBCLK, BMCLK)

9/25/08J. Lajoie - Muon Trigger Upgrade Review10 Base Board Design Base board design and layout nearly complete –Design in final stages at ISU –Many lessons learned from Tile design integrated into base board

9/25/08J. Lajoie - Muon Trigger Upgrade Review11 Schedule and Integration Rev2 Tiles Available Oct 20 th –Checkout at ISU to follow Base Board Schedule –Out for production Oct. 6 th –Assembled, in testing Oct. 27 th Algorithm Development/Programming –Underway through Jan. ’09 Basic trigger functionality at this point Integration at BNL Dec.’08-March’09