Bandgap Current Reference source: FEI4_A_CREF FEI4 collaboration. November 29, Vladimir Gromov NIKHEF, Amsterdam, the Netherlands

FEI4 collaboration V.Gromov229/11/09 The system requirements 22) The trim bits of the current reference will be modified to provide adjustment between nominal-30% and nominal+30%. Adjustment should only be possible in this narrow range. Setting the trim bits to 0 should not shut off the CREF, but simply set it to nominal-30%. 30% is not an exact requirement, could be 35% or 40% or 25% or something of that order. An extract from the document called “ Minutes-nov-11.pdf”, distributed by Maurice Garcia-Sciveres by E- mail on November (19:25) Subject: Re: CREF From: Abderrezak Mekkaoui Date: Wed, 11 Nov :18: To:, "ATLAS Pixel B-layer Replacement Electronics Replacement Electronics" Hi Vladimir/Ruud, The nominal is whatever you think the "optimal" should be based on the design (2.7uA according to the last year simulations). If it is 2uA then no problem. The only thing is that tuning should be done around the nominal value (not from 0 to max). ±1% (after tuning) would be very nice. ±5% acceptable. I hope this helps. Abderrezak On 11/11/2009 7:10 AM, Ruud Kluit wrote: Hello Abderrezak, VladimirG is busy doing the IC5 > IC6 cerversion of the CREF. During a recent (14th Oct.) phone meeting you mentioned that 2uA is the value as default for the CREF output. The tuning should be made such that all process corners can be tuned back to 2uA. This is what Vladimir did now. During the review you said 2.7uA..... So, you should be aware that the design is now optimized for 2uA. Regards, Ruud.

FEI4 collaboration V.Gromov329/11/09 FE_I4_A_CREF block: symbol Current output Analog VDD Analog GND (floating P-well) Substrate / Digital GND ( principal P-well) This output deliver current in the range 2.7uA ± 30% 1.92uA…3.6uA. The value is set by the control bits RefD Control bits (set the value of the current at Iref_out node)

FEI4 collaboration V.Gromov429/11/09 FE_I4_A_CREF block: schematic Optimal configuration has been chosen = the lowest Temperature gradient res_right = res1_5k and Res750 = res370 = DTMOST_72

FEI4 collaboration V.Gromov529/11/09 The layout Iref_out Analog VDD Analog GND (floating P-well) Substrate /Digital GND ( principal P-well) Control bits RefD 164um 204um

FEI4 collaboration V.Gromov629/11/09 The circuit Vdd Ib1 Ib2 Iref*= 26uA Ub1 Ub2 Ub3 Ub1 R2 R1 I2 I1 T1 T2 Iref = I1+I2 Iref RefD Iref*/2 = 15uAIref*/4 = 7uAIref*/8 = 3uA Iref_out= 1.92uA, …3.66uA Dynamic-threshold MOS transistor (DTMOST) Iref*= 52uA

FEI4 collaboration V.Gromov729/11/09 Curr_ref The top cell ( FEI4_A_CREF ) internally has the following configuration (found optimal in measurements) res_right = res1_5k and Res750 = res370 = DTMOST_72 Test bench A: schematic Iref_out=2.7uA, when RefD=1000 Temperature gradient is NOT optimal in simulation, and is well optimal according to the measurements

The top cell ( FEI4_A_CREF ) internally has the following configuration (found optimal in measurements) res_right = res1_5k and Res750 = res370 = DTMOST_72 Test bench A: temperature compensation Iref_out=2.7uA, when RefD=1000 Temperature gradient is NOT optimal in simulation, and is well optimal according to the measurements FEI4 collaboration V.Gromov829/11/09 Iref (Temp): simulations PTAT (I2) CTAT (I1) Currents Temp, [C] Iref (Temp): measurements

FEI4 collaboration V.Gromov929/11/09 Adjustment of the Iref_out Iref_out = uA RefD (1111) Iref_out = uA RefD (0111) Iref_out = uA RefD (0011) Iref_out = uA RefD (0001) Iref_out = 3.6uA RefD (0000)

FEI4 collaboration V.Gromov1029/11/09 Stability of the Iref_out Temperature scans at Vdd=1.1V, 1.2V, 1.3V RefD

FEI4 collaboration V.Gromov1129/11/09 Iref_out as a function of output voltage Vdd=1.2V and RefD [dI ref_out /I ref_out ] / d[V out ] = - 0.6% / V

-2.8μA ± 0.4μA (± 15%) FEI4 collaboration V.Gromov1229/11/09 Spread of the Iref_out: Mismatch + Process Temperature scans at Vdd= 1.2V RefD

FEI4 collaboration V.Gromov1329/11/09 Start-up of the circuit Monte-Carlo simulations. Mismatch only. The worst case. fixed_cor_sw = 7 Temp = -20°C no start-up failures

FEI4 collaboration V.Gromov1429/11/09 Test bench B This configuration guarantees the lowest Temp gradient in simulations and NOT in the measurements. Iref_out=1.88uA, when RefD=1000 Temperature gradient is optimal in simulation, and is NOT optimal according to the measurements

FEI4 collaboration V.Gromov1529/11/09 Lessons learned - when two adjustent cell have substrate connection RX+BP+CA+M1 (sub net) use SXCUT to run Assura LVS - do not use GRLOGIC as long as it masks GR110a (RX overlap past PC - silicide width) > 0.55u) - Use approapriate shapes when drawing PC in all gate around geometry. The cut must exclude corners<45°. Put an extra shape on it. -put more metal on VDD bus in order to avoid GR594 (For nets connected to NW contact, where the NW net is not connected to a substrate contact defined by ((RX over BP) not over (NW or RN or BB or JD or PI or T3)), the ratio of [ (20*Mx area) + (Non-isolated p+ junction area ((((RX over BP) over NW) not over PC) not over T3)) ] / (union[NW,PI] area) where x=1,2,3,4,5,6.) - Change size of the Bbox by editing rectangular in the layer chngLyr t0 - use layer called LVS:drawing1 in order to define triple well NFETs (nfettw) devices in layout - Please re-attach IBM library properties* to match current metal stack (it is now set at "6-2" instead of "3-2" and another property is missing): use menu item CIW>IBM_PDK>Library>Add IBM_PDK Lib Properties. - In fact it does not work like this. You need to check out (from the repository) file called data.dm - There is a noConn cell that should probably point to 'basic' cadence library rather then to your own lib. - Several cellnames contain a '.' character, which is an issue in Calibre but only when checking those cells as top cells - so don't bother fixing this. - to run DRC check in Calibre: - setting: BEOL_STACK = 3_2_3, TECHDIR = /user/foundry/vlsi/IBM/cmos8sf/IBM_PDK/relDM/Calibre - BURN_IN=empty, CHECK_RECOMENDED=ON, DENSITY_LOCAL=ON, DESIGN_TYPE=CELL, EXT_LATCHUP =JEDEC78, IOTYPE=WB_INLINE - use the following runset /project/et/Atlas/Upgrade/InnerTracker/PixelDet/cadence/FE_I4_bandgap/vgromov_05_01_10.drc, - to run LVS check in Calibre: - Setting: COMPARE_NF_VALUES=FALSE, LASTMETAL=MA, MGPROCESS=MG, NO_SUBC_IN_GRLOGIC=TRUE, NO_TRACE_PROPERTY=FALSE, NUMMETAL=8, PEX_RUN=FALSE, PWELL_SUBC_DEVICE=FALSE, USE_RESISTANCE_MULTIPLIERS=TRUE. - use the following runset - /project/et/Atlas/Upgrade/InnerTracker/PixelDet/cadence/FE_I4_bandgap/lvs_gromov_06_01_10.runset - this runset generate all the netlist files when choose: Export from layout viewer=ON and Export from schematic viewer=ON

FEI4 collaboration V.Gromov1629/11/09 Lessons learned - RULE FILE: /project/et/Atlas/Upgrade/InnerTracker/PixelDet/cadence/FE_I4_bandgap/CalibreLVS/_cmrf8sf.lvs.cal_ - Check LVS setting in : /project/et/Atlas/Upgrade/InnerTracker/PixelDet/cadence/FE_I4_bandgap/example.lvs.report - When parallel MOST’s are not of the same size they will be seen as two different devices in layout and as one device in schematic. This causes LVS discrepancy. Put resistors (opndres_inh) in series with the gate connection in order to make two device in schematic too. This will solve the problem. - put two labels in sub.drw and SXCUT.lbl layer in order to stamp the substrate with nothing under Connectivity>Net name (assigns name sub! to substrate) - in schematic use nfet_inh devices when you want to give the name sub! to the substrate. - use subc component : put SUBCON net name on the net connected to SUBCON pin and inherited name on the net connected to the sub pin as follows: - Add Wire Name> Net Expression> Property Name = substrate and Default Net Name = sub! (then the global net sub! will be present in all the blocks and no dedicate pin is needed in schematic only) - Put a note on the symbol view to order to make it clear which cell is this (use Create>Note>Text> FontHeight=0.2, Font Style=roman do not forget that the value of the output current will be 40% higher when you change the setting from res_right = res1_5k (optimal operational point in simulations) to res_right = res1_5k + Res750 = res370 = DTMOST_72 (optimal point found in the measurements) Take it into account when you calculate the size ratio in the current mirrors. if res_right = res1_5k then Iout_largest = 26.11uA in simulation and 30.3uA in the measurements if res_right = res1_5k + Res750 = res370 = DTMOST_72 then Iout_largest = 39.79uA in simulation and 43.7uA in the measurements -