Serial Data Link on Advanced TCA Back Plane M. Nomachi and S. Ajimura Osaka University, Japan CAMAC – FASTBUS – VME / Compact PCI What ’ s next?

Slides:



Advertisements
Similar presentations
1 iTOP Electronics Effort LYNN WOOD PACIFIC NORTHWEST NATIONAL LABORATORY JULY 17, 2013.
Advertisements

On the development of the final optical multiplexer board prototype for the TileCal experiment V. González Dep. of Electronic Engineering University of.
TileCal Optical Multiplexer Board 9U VME Prototype Cristobal Cuenca Almenar IFIC (Universitat de Valencia-CSIC)
1 SpaceWire Router ASIC Steve Parkes, Chris McClements Space Technology Centre, University of Dundee Gerald Kempf, Christian Toegel Austrian Aerospace.
E-link IP for FE ASICs VFAT3/GdSP ASIC design meeting 19/07/2011.
SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.
ESODAC Study for a new ESO Detector Array Controller.
CMS Week Sept 2002 HCAL Data Concentrator Status Report for RUWG and Calibration WG Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University.
SciFi Tracker DAQ M. Yoshida (Osaka Univ.) MICE Tracker KEK Mar. 30, 2005.
An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment H.XU, Z.-A. LIU,Q.WANG, D.JIN, Inst. High Energy Physics, Beijing, W. Kühn, J. Lang, S.
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented.
PALM-3000 P3K FPDP Carrier Board Review Dean Palmer Building 318, Room 125 November 10, :00 am – 12:00 pm.
6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.
Takeo Higuchi Institute of Particle and Nuclear Studies, KEK; On behalf of COPPER working group Jan.20, 2004 Hawaii, USA Super B Factory Workshop Readout.
Programmable logic and FPGA
Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.
HCAL FIT 2002 HCAL Data Concentrator Status Report Gueorgui Antchev, Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University.
Data acquisition system on Advanced TCA M. Nomachi and S. Ajimura Osaka University, Japan CAMAC – FASTBUS – VME / Compact PCI What ’ s next?
PCIe based readout U. Marconi, INFN Bologna CERN, May 2013.
Status of LAV FEE electronics G. Corradi, C. Paglia, D. Tagnani & M. Raggi, T. Spadaro, P. Valente.
First Paper in 1984 on FADCS FADC Cost Power RAM Power ECL TTL Narrow & Deep Need: Wide & Shallow More Expensive then FADC.
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
TRIGGER-LESS AND RECONFIGURABLE DATA ACQUISITION SYSTEM FOR POSITRON EMISSION TOMOGRAPHY Grzegorz Korcyl 2013.
NEDA collaboration meeting at IFIC Valencia, 3rd-5th November 2010 M. Tripon EXOGAM2 project Digital instrumentation of the EXOGAM detector EXOGAM2 - Overview.
SBS meeting VETROC application for Cerenkov triggering Alexandre Camsonne March 18 th 2015.
Understanding Data Acquisition System for N- XYTER.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź LLRF review, DESY, 3-4 December 2007 Advanced.
SBS meeting VETROC application for Cerenkov triggering Alexandre Camsonne March 18 th 2015.
Detectors and read-out DetectorNo. of ch.Read-out method Device candidates CsI(Tl)768Flash ADCCOPPER + 65 MHz FADC FINESSE Active Polarimeter600 x 12 x.
A Readout Electronics for MAPMT Matteo Turisini – E. Cisbani Italian National Institute of Health – INFN Rome 1 JLab/CLAS12 RICH Meeting - 16/Nov/2011.
DAQ Issues for the 12 GeV Upgrade CODA 3. A Modest Proposal…  Replace aging technologies  Run Control  Tcl-Based DAQ components  mSQL  Hall D Requirements.
Agata Week – LNL 14 November 2007 Global Readout System for the AGATA experiment M. Bellato a a INFN Sez. di Padova, Padova, Italy.
Leo Greiner IPHC DAQ Readout for the PIXEL detector for the Heavy Flavor Tracker upgrade at STAR.
David Abbott - JLAB DAQ group Embedded-Linux Readout Controllers (Hardware Evaluation)
Status of Global Trigger Global Muon Trigger Sept 2001 Vienna CMS-group presented by A.Taurok.
FADC progress in Vienna Reported by H.Ishino for Vienna FADC group M.Pernicka and H.Steininger.
11th March 2008AIDA FEE Report1 AIDA Front end electronics Report February 2008.
CPT Week, April 2001Darin Acosta1 Status of the Next Generation CSC Track-Finder D.Acosta University of Florida.
Gueorgui ANTCHEVPrague 3-7 September The TOTEM Front End Driver, its Components and Applications in the TOTEM Experiment G. Antchev a, b, P. Aspell.
First ideas for the Argontube electronics Shaper, simulations Block Diagram for analog path Delta Code Data Reduction Bus system, Controller Max.
Owner: VBHUSales Training 03/15/2013 Cypress Confidential IDT 72T36135M vs. Cypress CYF072x Video Buffering Applications High density FIFOs with unmatched.
Xiangming Sun1PXL Sensor and RDO review – 06/23/2010 STAR XIANGMING SUN LAWRENCE BERKELEY NATIONAL LAB Firmware and Software Architecture for PIXEL L.
Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.
1 FADC Boards for JPARC-K Preliminary Proposal Mircea Bogdan November 16, 2006.
NUMI Off Axis NUMI Off Axis Workshop Workshop Argonne Meeting Electronics for RPCs Gary Drake, Charlie Nelson Apr. 25, 2003 p. 1.
Latest ideas in DAQ development for LHC B. Gorini - CERN 1.
Towards a final design of LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.
1/12/2010 R. CIARANFI 1 NEW NINO BOARD FOR RICH OLD AND NEW LOGISTIC NEW BOARD DESCRIPTION NEW MODULARITY 32 CH NEW FORM FACTOR FRONT END AREA AND DAQ.
Sep. 17, 2002BESIII Review Meeting BESIII DAQ System BESIII Review Meeting IHEP · Beijing · China Sep , 2002.
1 April 2009 NA62 DAQ meeting1 LKr calorimeter readout project H.Boterenbrood, A.Ceccucci, B.Hallgren, M.Piccini, H. Wendler.
SoLiD/PVDIS DAQ Alexandre Camsonne. DAQ limitations Electronics Data transfer.
CM19 Vassil Verguilov DAQ Status  Progress  DAQ  Next steps  Summary.
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
Development of PCI Bus Based DAQ Platform for Higher Luminosity Experiments T.Higuchi, 1 H.Fujii, 1 M.Ikeno, 1 Y.Igarashi, 1 E.Inoue, 1 R.Itoh, 1 H.Kodama,
XLV INTERNATIONAL WINTER MEETING ON NUCLEAR PHYSICS Tiago Pérez II Physikalisches Institut For the PANDA collaboration FPGA Compute node for the PANDA.
Peter LICHARD CERN (NA62)1 NA62 Straw tracker electronics Study of different readout schemes Readout electronics frontend backend Plans.
Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao.
1 Carleton/Montreal Electronics development J.-P Martin (Montreal) Shengli Liu & M. Dixit (Carleton) LC TPC Meeting DESY Hamburg, 4 June 2007.
ROM. ROM functionalities. ROM boards has to provide data format conversion. – Event fragments, from the FE electronics, enter the ROM as serial data stream;
X SuperB Workshop - SLAC Oct 06 to Oct 09, 2009 A.Cotta Ramusino, INFN Ferrara 1 SuperB IFR: outline of the IFR prototype electronics A.C.R
Firmware development for the AM Board
Testing PCI Express Generation 1 & 2 with the RTO Oscilloscope
Production Firmware - status Components TOTFED - status
Iwaki System Readout Board User’s Guide
System On Chip.
Read-out of High Speed S-LINK Data Via a Buffered PCI Card
VELO readout On detector electronics Off detector electronics to DAQ
PID meeting Mechanical implementation Electronics architecture
Presentation transcript:

Serial Data Link on Advanced TCA Back Plane M. Nomachi and S. Ajimura Osaka University, Japan CAMAC – FASTBUS – VME / Compact PCI What ’ s next?

RT2005 Nomachi, M.2 CAMAC crate Downsizing (Rack-Crate-Module-Chip-) CPU BUS module

RT2005 Nomachi, M.3 Module Downsizing (Rack-Crate-Module-Chip-) Is CPU at right place? Should we have parallel BUS on board? Do we still need crate? CPU BUS FPGA Network Interface Questions

RT2005 Nomachi, M.4 Functionality of a CPU Data readout –Register/memory access –Block transfer Data processing –Application dependent Network protocol –TCP/IP etc. –It is indispensable function for network DAQ. CPU sits at the boundary between memory mapped I/O and network

RT2005 Nomachi, M.5 Rack Crate Module Chip Memory Mapped I/O CPU Network DAQ architecture Memory Mapped I/O CPU Network CPU Network

RT2005 Nomachi, M.6 Rack Crate Module Chip Memory Mapped I/O CPU Network DAQ architecture We choose memory mapped I/O in a crate. It makes easy to maintain CPU. There were many bad experiences on embedded CPUs.

RT2005 Nomachi, M.7 Downsizing the interconnections Parallel bus on board –Occupy large area –Need many pins Serial data link will be a solution –It can be low noise/low power Less number of drivers –It may have longer latency 1 ns – 100 ns. Memory mapped I/O over serial data link.

RT2005 Nomachi, M.8 SpaceWire Remote Memory Access Protocol (RMAP) SpaceWire was presented by S. Parkes. –RMAP is a protocol on the SpaceWire standard. –Register access has large overhead. –Block transfer works almost full speed. –It meets the requirements. Good enough. –PCI express and the other protocol may also meet the requirements. However, they may use too much logic (x10) for front-end FPGAs.

RT2005 Nomachi, M.9 Do we need crate? Serial data link is very flexible. –System with no crate is possible. Functionality of crates: 1.Mechanical Housing / Shielding 2.Power supply 3.Cooling –We need a crate. VME –6U is too small –Power is a problem on VME. -5.2V etc.

RT2005 Nomachi, M.10 Advanced TCA Features (ATCA was presented by B. Martin and S. Dhawan) –-48V DC power supply and on board DC converter for any voltages required. –8U x 280 mm –Dual Star point to point differential connection –No definite protocol. VME back plane is for VME protocol. While, ATCA back plane is only defined as 100 ohm differential. Any protocol can use ATCA back plane. ( for example, ATCA for physics instrumentation)

RT2005 Nomachi, M.11 Read out module Trigger module Front-end module DAQ system Front-end Pipe-line buffer readout buffer Trigger logic Trigger control Global trigger Readout control network Second level trigger CPU To event builder

RT2005 Nomachi, M.12 Dual star connection Trigger module Read out module Front-end module Front-end module Front-end module Front-end module Front-end module Asynchronous signals (4 links) Trigger/Reset Local trigger/Busy SpaceWire link (4 links) CPU (T-kernel)

RT2005 Nomachi, M.13 There are 4 ports for one channel. One port has one output and one input. In order to make signal extraction easy, 2 ports are used. (SpW uses 2 ports) The other 2 ports are to extend band width. It makes possible to use 4-layers PCBs.

RT2005 Nomachi, M.14 Trigger module 16 LVDS in 16 LVDS out 8 NIM in 8 NIM out Power consumption is about 10W Cyclone EP1C12 for trigger logic Cyclone EP1C6 for SpW 100Mbps SpW

RT2005 Nomachi, M MHz FADC Cyclone EP1C6 (cheaper than 40 Euro) Cyclone EP1C12 for router 100Mbps SpW (8~9 MB/s from the module) Readout buffer with 128Mb SDRAM waiting second level trigger 8 ch analog input FADC mezzanine card is developed at KEK (FINESSE format) Power consumption is About 20W

RT2005 Nomachi, M.16 ATCA crate One crate holds 96ch of 500MHz FADCs. Total power is expected to be 260 W.

RT2005 Nomachi, M.17 Summary SpaceWire Remote Memory Access Protocol provides compact and flexible interconnection in a module and inter- module connection. Advanced TCA provide dual star LVDS connections. They are good to be applied for DAQ system Downsizing may continue. –We might have another solution in the future.