Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems.

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Presentation transcript:

Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems and Applications

Lecture 12: Reconfigurable Systems II October 20, 2004 Overview Types of Reconfigurable Computing Systems Main focus: two pioneering systems: Splash + PAM Important synergy between hardware and software Super computer speedups for several applications.

Lecture 12: Reconfigurable Systems II October 20, 2004 Important System Issues Computation philosophy System Architecture External interface Verification Programming environment.

Lecture 12: Reconfigurable Systems II October 20, 2004 Programmable Active Memory Developed by DEC Paris Research Group ( ) Attached to DEC workstation via Turbochannel bus interface for burst transfers. Total of 12 manufactured and distributed worldwide. Flexible software environment.

Lecture 12: Reconfigurable Systems II October 20, 2004 Hybrid Architecture Buses connect groups of FPGAs to SRAM Extra devices used for RAM controller and map to external interface.

Lecture 12: Reconfigurable Systems II October 20, 2004 Computational Model Communication protocol between devices defined by user program. Virtual machine defined by configuration bitstream that determines functionality. Treated like a memory by host machine software [read and write]. PAM evaluates inputs, generates outputs.

Lecture 12: Reconfigurable Systems II October 20, 2004 Programming Environment Pam program consists of three parts: 1.Driving software which runs on the host and controls PAM hardware. 2.Logic equations describing synchronous hardware implemented on PAM board. 3.Place and route directives that guide implementation of logic equations onto PAM board. Driving software written in C or C++ and linked to runtime library All design synchronous.

Lecture 12: Reconfigurable Systems II October 20, 2004 Programming Environment Firmware consists of stock interfaces to memory and workstation interface. Designs described algorithmically at structural level. Annotated with placement information. User simulates entire design Hardware/software co-debug: slowly transition algorithm representation to hardware.

Lecture 12: Reconfigurable Systems II October 20, 2004 Programming Example Structural description written in C++ Translated to a netlist

Lecture 12: Reconfigurable Systems II October 20, 2004 Debugging Steps Simulate design using RTL-like verification Model application including interface driver and bus Implement application in hardware-single step with help of read-back option. Apply numerous test vectors to design to fully evaluate functionality.

Lecture 12: Reconfigurable Systems II October 20, 2004 Network Routing FPGAs popular in network hardware New protocols implemented directly in silicon Easy to upgrade in the field Washington University Gigabit Switch (WUGS) -Switch provides up to 160 Gbps of bandwidth.

Lecture 12: Reconfigurable Systems II October 20, 2004 FPGA-based Router FPX module contains two FPGAs NID – network interface device -Performs data queuing RAD – reprogrammable application device -Specialized control sequences

Lecture 12: Reconfigurable Systems II October 20, 2004 Reconfigurable Data Queuing Data may be congested. FPGA can be programmed for virtual channels.

Lecture 12: Reconfigurable Systems II October 20, 2004 Hardware Setup Stacked boards part of system Scalable to multiple boards Allows for cooling, power.

Lecture 12: Reconfigurable Systems II October 20, 2004 IP Lookup Function RAD can be used to evaluate packet headers. Headers evaluated in groups of four bits

Lecture 12: Reconfigurable Systems II October 20, 2004 RAD Functionality Packet decode occurs every 38 cycles at 10ns RAD can be dynamically reconfigured.

Lecture 12: Reconfigurable Systems II October 20, 2004 Smart Port Card Smart port card contains Pentium processor Used for special data conditions -Address translation -Virus detection Provides for hardware/software approach

Lecture 12: Reconfigurable Systems II October 20, 2004 Summary Several applications: logic emulation and networking discussed so far: more to come. Early software systems require primarily low-level programming to ensure reasonable utilization and performance Debugging environment at several levels important to rapid design development As systems mature, need for high-level compilation becomes critical.