1 Low-Voltage BiCMOS Circuits for High-Speed Data Links up to 80 Gb/s Tod Dickson University of Toronto June 24, 2005.

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Presentation transcript:

1 Low-Voltage BiCMOS Circuits for High-Speed Data Links up to 80 Gb/s Tod Dickson University of Toronto June 24, 2005

T. Dickson University of Toronto June 24, Low-Voltage, Low-Power Techniques High-speed CML/ECL latch BiCMOS logic family reduces supply voltage Inductive peaking L P = CLV2CLV2 3.1 I T 2

T. Dickson University of Toronto June 24, V, 49-Gb/s Decision Circuit DFF 49-Gb/s Data In 49-Gb/s Data Out 49-GHz CLK Flip-flop core consumes 58 mW. 2 x 600mV output 49-Gb/s. Inductors smaller than bond pad.

T. Dickson University of Toronto June 24, Gb/s PRBS Generator 80-Gb/s output eye diagram Die Photo Output Spectrum Highest level of single-chip integration above 40-Gb/s

T. Dickson University of Toronto June 24, V, 80-Gb/s BiCMOS Pre-Emphasis Driver Adjustable pre-emphasis for operation up to 80-Gb/s Boosts high-frequency content to compensate for line losses. Output match S22 < -10dB up to 94 GHz. First silicon amplifier with gain above 90-GHz.