KIP Ivan Kisel JINR-GSI meeting Nov 2003 High-Rate Level-1 Trigger Design Proposal for the CBM Experiment Ivan Kisel for Kirchhoff Institute of Physics, Uni-Heidelberg, Germany Laboratory of Information Technologies, JINR, Dubna, Russia Level-1 Trigger: Concept Prototype Simulation Reconstruction

KIP Ivan Kisel JINR-GSI meeting Nov 2003 ObjectivesObjectives 1.High performance farm test bed Test most of aspects of the system using detector mock-ups. 2.MHz cluster resource management  Resource management, scheduling algorithm and infrastructure. 3.MHz reliable low-cost networking framework (ATOLL, SCI, Infiniband, …)  At least two NIC candidates are planned to be evaluated. At least one NIC will then be implemented in the prototype. 4.Cluster fault tolerance framework  Automatic remedy to most error conditions without human intervention or isolation and documentation for irreparable errors. 5.MHz cluster simulation Test all possible operating aspects as well as scalability of the system. 6.Level-1 reconstruction algorithm  High speed algorithm for triggering. 7.FPGA co-processor framework  FPGA co-processor will implement bus snooping techniques. We propose the development of a generic, modular, high rate, high throughput, reliable commodity compute farm infrastructure and prototype for the specific requirements of the CBM experiment. The scalability is demonstrated by appropriate simulations. The prototype farm is to be subjected to regular use by the collaboration for simulation in parallel to the real-time on-line performance testing and monitoring.

KIP Ivan Kisel JINR-GSI meeting Nov 2003 Sketch of Data Flow and Data Topology IT TOF Reaction Counter RICH TRD Tracklet search Cluster search Readout L1 TMU L2 Algorithm HLT / DAQ Ring searchL1L2DAQ IT-Vertex Processor Local processing Sub-event building Event processing

KIP Ivan Kisel JINR-GSI meeting Nov D Topology RU Sch TRD Input Data x y z RU RICH IT TOF TRD RICH IT TOF PC Farm TagNet

KIP Ivan Kisel JINR-GSI meeting Nov 2003 A Compute Node NIC PCI bus CPU In Out ATOLL  ATOLL  SCI Infiniband  Infiniband  … ATOLL  ATOLL  SCI Infiniband  Infiniband  … FPGA

KIP Ivan Kisel JINR-GSI meeting Nov 2003 Level-1 Trigger Prototype in Heidelberg >1 MHz 32 dual CN 2D torus 6 Gb/s 2D SCI 480 MB/s p-p 450 MB/s x-y 1 Gb/s Ethernet

KIP Ivan Kisel JINR-GSI meeting Nov 2003 Automatic setup of the compute farm Configure and control processes on every CN GUI of Prototype

KIP Ivan Kisel JINR-GSI meeting Nov 2003 Hardware Initiated DMA Transfer

KIP Ivan Kisel JINR-GSI meeting Nov 2003 Ptolemy II Simulation of the Trigger

KIP Ivan Kisel JINR-GSI meeting Nov 2003 TRACK RECONSTRUCTION based on the Cellular Automaton Method XZ (bending) / YZ (non-bending) TRACK RECONSTRUCTION based on the Cellular Automaton Method XZ (bending) / YZ (non-bending)

KIP Ivan Kisel JINR-GSI meeting Nov 2003 TRACKING EFFICIENCY RECO STATISTICS 100 events Refprim efficiency : | Refset efficiency : | Allset efficiency : | Extra efficiency : | Clone probability : | 7 4 Ghost probability : 5.18 | 3358 Reco MC tracks/event : 6 48 Timing/ event : 175 ms RECO STATISTICS 100 events Refprim efficiency : | Refset efficiency : | Allset efficiency : | Extra efficiency : | Clone probability : | 7 4 Ghost probability : 5.18 | 3358 Reco MC tracks/event : 6 48 Timing/ event : 175 ms ALL MC TRACKS RECONSTRUCTABLE TRACKS Number of hits >= 3 REFERENCE TRACKS Momentum > 1 GeV TIMING (ms) Fetch ROOT MC data 63.3Copy to local arrays and sort Create and link segments Create track candidates Select tracks 2.6 TIMING (ms) Fetch ROOT MC data 63.3Copy to local arrays and sort Create and link segments Create track candidates Select tracks 2.6 FPGA Co-processor 98% CPU 2% CA – INTRINSICALLY LOCAL AND PARALLEL CA – INTRINSICALLY LOCAL AND PARALLEL

KIP Ivan Kisel JINR-GSI meeting Nov 2003 Plans:Plans: Kirchhoff Institute of Physics, Uni-Heidelberg, Germany Laboratory of Information Technologies, JINR, Dubna, Russia Develop Architecture with 3D topology and TagNet.  Heidelberg (3) Develop Scheduler.  Heidelberg (1) Investigate the Prototype of 32 dual CNs at > 1 MHz.  Heidelberg (2) Advance the Simulation based on the prototype measurements.  Dubna (2) Investigate different Network Interface Cards applicability.  Heidelberg (3) + Dubna (2) Develop the Reconstruction algorithm.  Heidelberg (1) + Dubna (4)