An Effective Congestion Driven Placement Framework André Rohe University of Bonn, Germany joint work with Ulrich Brenner.

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Presentation transcript:

An Effective Congestion Driven Placement Framework André Rohe University of Bonn, Germany joint work with Ulrich Brenner

A dense Placement good wirelength impossible to route

Possible Solution easy to route bad wirelength/timing

Congestion Driven Placement easy to route + good wirelength almost no extra computation efford !

Our Basis: Bonn Place Partitioning based approach Solves QP in each level, followed by partitioning Partitioning is done by quadrisection: circuits are partitioned with minimum movement (Vygen)

Methods used for congestion driven placement Very fast congestion calculation Inflate circuits in congested regions Spreading inflated cells

Congestion calculation Calculate Steiner Tree for each net Probablitiy estimation for each 2-point connection (similar to Hung & Flynn, Lou et al.)

Quality of congestion calculation congestion estimation

Quality of congestion calculation Bonn Global HDP Global

Inflation of circuits (used previously by Hou et al.) Initial inflation (based on pin density) Given a circuit c in Region R, c is inflated by up to 100% The inflation is based on the congestion in R and the surrounding regions & the pin density in R Deflation is possible if the circuit is no longer critical.

Placement Step 0

Placement Step 1

Placement Step 2

Placement Step 3

Placement Step 4

Placement Step 5

Placement Step 6

Placement Step 7

Spreading inflated cells Repartitioning considers 2x2 windows in placement grid to optimize netlength Use extra repartitioning step to move cells away from overloaded regions

Summary: Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Repartitioning 3.Legalization

Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} For (each c in {all circuits}) Increase b(c) proportionally to |pins(c)|/size(c) # initial inflation b(c) 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Repartitioning 3.Legalization

Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} For (each c in {all circuits}) Increase b(c) proportionally to |pins(c)|/size(c) # initial inflation b(c) 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Compute congestion and update b(c) # update inflation b(c) Quadrisection(w) Repartitioning 3.Legalization

Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} For (each c in {all circuits}) Increase b(c) proportionally to |pins(c)|/size(c) # initial inflation b(c) 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Compute congestion and update b(c) # update inflation b(c) Quadrisection(w) Reduce overloaded windows # extra repartitioning steps Repartitioning 3.Legalization

Computational Results I ChipTech|Nets|DensityGridsizeRelease IBM 1sa2773, % 4091x3563x IBM 2sa1273, % 6118x6119x IBM 3sa27426, % 26792x26792x IBM 4sa27706, % 14028x13110x IBM 5sa271,390, % 23912x23912x7 2001

Computational Results II StandardCongestion Driven ChipCPUlenCPUlenBlow IBM 10:23 h7.2 m0:26 h7.4 m10.2 % IBM 20:26 h7.9 m0:27 h9.0 m6.6 % IBM 33:50 h134 m4:39 h142 m20.1 % IBM 47:08 h241 m7:24 h270 m20.2 % IBM 516:10 h375 m16:37 h406 m57.8 %

Computational Results II StandardCongestion Driven ChipCPUlenCPUlenBlow IBM 10:23 h7.2 m0:26 h7.4 m10.2 % IBM 20:26 h7.9 m0:27 h9.0 m6.6 % IBM 33:50 h134 m4:39 h142 m20.1 % IBM 47:08 h241 m7:24 h270 m20.2 % IBM 516:10 h375 m16:37 h406 m57.8 % Mean+8.7 %+8.5%

Computational Results III StandardCongestion Driven ChipHDPovCPUlenHDPovCPUlen IBM :15 h9 m75.500:05 h7.5 m IBM :19 h11.5 m75.400:05 h10.1 m IBM :36 h162 m77.304:51 h164 m IBM :18 h324 m75.202:48 h326 m IBM :57 h512 m :48 h527 m

Computational Results III StandardCongestion Driven ChipHDPovCPUlenHDPovCPUlen IBM :15 h9 m75.500:05 h7.5 m IBM :19 h11.5 m75.400:05 h10.1 m IBM :36 h162 m77.304:51 h164 m IBM :18 h324 m75.202:48 h326 m IBM :57 h512 m :48 h527 m Mean-9 %-73 %-5.2 %

Thank you for your attention !