Increasing Cache Efficiency by Eliminating Noise Prateek Pujara & Aneesh Aggarwal {prateek, State University of New York, Binghamton

INTRODUCTION Caches are very important to cover the processor-memory performance gap. Thus Caches should be utilized very efficiently. Fetch only the useful data Cache Utilization : Percentage of the useful words out of the total words fetched into the cache.

Utilization vs Block-Size Larger Cache Blocks Increase bandwidth requirement Reduce utilization Smaller Cache Blocks Reduces bandwidth requirement Increase utilization

Percent Cache Utilization 16KB, 4-way Set Associative Cache, 32 byte block size

Methods to improve utilization Rearrange data/code Dynamically adapt cache line size Sub-blocking

Benefits of Utilization improvement Lower energy consumption By avoiding wastage of energy on useless words. Improve performance By better utilizing the available cache space. Reduce memory traffic By not fetching useless words.

Our Goal Improve Utilization Predict the to-be-referenced words Avoid cache pollution by fetching only the predicted words

Our Contributions Illustrate high predictability of cache noise Propose efficient cache noise predictor Show potential benefits of cache noise prediction based fetching in terms of Cache utilization Cache power consumption Bandwidth requirement Illustrate benefits of cache noise prediction for prefetching Investigate cache noise prediction as an alternative to sub-blocking

Cache Noise Prediction Programs repeat the pattern of memory references. Predict cache noise based on the history of words accessed in the cache blocks.

Cache Noise Predictors 1) Phase Context Predictor (PCP) Records the words usage history of the most recently evicted cache block. 2) Memory Context Predictor (MCP) Assuming that data accessed from contiguous memory locations will be accessed in same fashion. 3) Code Context Predictor (CCP) Assuming that instructions in a particular portion of the code will access data in same fashion.

Cache Noise Predictors For code context predictors Use higher order bits of PC as context Store the context along with the cache block. Add 2 bit vectors for each cache block One for identifying the valid words present One for storing the access pattern

Code Context Predictor (CCP) Say PC of an instruction is

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Code Context:

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Code Context: Last Word Usage History Valid-Bit

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (xxxxxx) Y (101001) x x 11 0 Code Context:

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (xxxxxx) Y (101001) x x 11 0 Code Context: Miss due to PC Only 1st and 2nd words are brought Evicted cache block was brought by PC and used only 1st word

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (xxxxxx) Y (101001) x x 11 0 Code Context: Miss due to PC Only 1st and 2nd words are brought Evicted cache block was brought by PC and used only 1st word

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (101110) Y (101001) Code Context:

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (101110) Y (101001) Code Context: Miss due to PC Only 1st word brought Evicted block was brought by PC and used 2nd and 4th word

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (101110) Y (101001) Code Context: Miss due to PC Only 1st word brought Evicted block was brought by PC and used 2nd and 4th word

Code Context Predictor (CCP) Say PC of an instruction is X (100110) Z (101110) Y (101001) Code Context:

Predictability of CCP PCP - 56% MCP - 67% Predictability = Correct prediction/Total misses No prediction almost 0%

Improving the Predictability Miss Initiator Based History (MIBH) Words usage history based on the offset of the word that initiated the miss. ORing Previous Two Histories (OPTH) Bitwise ORing past two histories.

Predictability of CCP The predictability of PCP and MCP was about 68% and 75% respectively using both MIBH and OPTH.

CCP Implementation context valid-bit words history usage

CCP Implementation words history words history usage context valid-bit MIWO MIWO -- Miss Initiator Word Offset

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

CCP Implementation read/write port words history words history usage context valid-bit MIWO broadcast tag MIWO -- Miss Initiator Word Offset = ==

Experimental Setup Applied noise prediction to L1 data cache L1 Dcache of 16KB 4-way associative 32byte block size Unified L2 cache of 512KB 8-way associative 64 byte block size L1 Icache of 16KB direct mapped ROB instructions LSB - 64 entries Issue Queue - 96 Int/64 FP

Prediction Accuracies with 32/4, 16/8 & 16/4 CCP 32/416/816/4

RESULTS

Percentage Dynamic Energy Savings

Prefetching Processors employ prefetching to improve the cache miss rate. Fetch the next cache block on a miss to exploit spatial locality. The prefetched cache block is predicted to have the same pattern as that of the currently fetched block.

Prefetching Prefetched cache block updates the predictor table when evicted. Prefetched cache block is stored without any context information Whenever it is accessed for the first time, the context and the offset information is stored Prefetched block does not update the predictor table when evicted.

Prediction Accuracy with Prefetching Energy consumption reduced by about 22% Utilization increased by about 70% Miss Rate increased only by about 2% No Prefetching No Update Update

Sub-blocking Sub-blocking is used to Reduce cache noise Reduce bandwidth requirement Limitations of sub-blocking Increased miss rate Can we use cache noise prediction as an alternative to sub-blocking?

Cache Noise Prediction vs Sub-blocking

Conclusion Cache noise is highly predictable. Proposed cache noise predictors. CCP achieves 75% prediction rate with correct prediction of 97% using a small 16 entry table. Prediction without impact on IPC and minimal impact (0.1%) on miss rate. Very effective with prefetching. Compared to sub-blocking cache noise prediction based fetching improves Miss rate by 97% and Utilization by 10%

QUESTIONS ??? Prateek Pujara & Aneesh Aggarwal {prateek, State University of New York, Binghamton