1 Basic MOS Device Physics

2 Concepts understanding of semiconductor devices is essential in analog IC design  Performance affected by second order effects,  often neglected in digital design More for deep submicron technologies Develop transistor model for circuit performance and analysis  MOS structure, IV characteristics, second order effects, parasitic capacitances, small-signal model for MOSFET,SPICE model

3 MOS Device Structure Structure: 2 heavily-doped n regions defining D and S, heavily-doped polysilicon forming G, thin layer of oxide insulating G from substrate Useful action occurs in substrate region under gate oxide 4-terminal device, with S and D interchangable Digital IC: transistor acts like a switch Turns on (S and D “connected together”) when V G high, off when V G low

4 NMOS and PMOS with Well CMOS – both NMOS and PMOS available on the same substrate  Ok for NMOS, but PMOS must define a local n- substrate -> n-well NMOS: S/D junction must be reverse-biased -> substrate connected to most negative supply voltage PMOS: S/D junction must be reverse-biased -> substrate connected to most positive supply

5 MOS Symbols

6 triode region I-V characteristic Triode region when V DS <= V GS - V TH

7 Operation in Triode Region -> I D linear function of V DS Parabola approximated by straight line. S-D can now be modelled as a linear controlled-resistor given by V DS /I D and value controlled by overdrive voltage (V GS – V TH )

8 Active Region (cont.) Active Region

9 If V DS > V GS -V TH ?  I/V curve no longer parabolic  I D constant, device in saturation/active region  Density of inversion layer proportional to V GS – V(x) – V TH  If V DS slightly greater that V GS – V TH, inversion layer stops at x <= L; i.e. channel is pinched off  As V DS increases further Point at which Q d equals zero gradually moves toward S Operation in Active (Saturation) Region

10 Drain current characteristics

11 Drain current Linear region (V ds < V gs - V t ):  I d = k’ (W/L)(V gs - V t )(V ds V ds 2 ) Saturation region (V ds >= V gs - V t ):  I d = 0.5k’ (W/L)(V gs - V t ) 2

12 MOS operation conclusion region V G condition V DS condition ID OFF V G < V TH Any value0 TRIODE/ LINEAR V G >V TH V DS < V DS -V TH  n C ox W/L (V DS - V TH )V DS – 0.5V DS 2 SATURAT ION V G >V TH V DS > V DS -V TH 0.5  n C ox W/L (V DS - V TH ) 2

13 Transconductance, g m Let’s define g m as an indicator of how well a device converts a voltage to a current (consider saturation region) g m represents device sensitivity  e.g. small change in V GS results in large change in I D  As seen in eqn above, g m is equal to inverse of R on in deep triode region

14 g m behavior – from g m plot Notice:  g m increases with overdrive if W/L constant  g m decreases with overdrive if I D constant

15 Triode and Active Region Transition Rule of thumb when trying to know if device is in saturation or linear  NMOS: V G - V D < V THN, pinch-off occurs  PMOS: V D – V G < |V THP |, saturation Active

16 Second-Order Effects Now let’s look at second order effects and get some idea on how our circuit could be affected by the phenomena

17 Body Effect What happens when bulk and source are not at the same potential Consider NMOS: When V B drops below V S  S and D still reverse-biased -> device continues to operate properly but some device properties might change  e.g. V S =V D =0; V G a bit less than V TH -> depletion layer formed but no inversion layer As V B becomes more negative -> more holes attracted to substrate connection, leaving larger –ve charge behind (i.e. depletion region becomes wider) V TH = f(total charge in depln region), and gate charge must mirror Q d (channel charge density) before an inversion layer formed V B drops, Q d increases, V TH increases -> “Body effect” / “Backgate” Effect

18 Body Effect …  denotes body effect coefficient  Typical values: 0.3 to 0.4V 1/2 Could take place when:  Bulk potential change  Source potential varies wrt bulk potential

19 No Body Effect With Body Effect Ignore body effect:  As V in varies, V out closely follows the input Drain current remains I 1 I 1 =0.5  n C ox (W/L)(V in -V out -V TH ) 2 i.e. (V in -V out ) is constant if I 1 is constant Body effect significant, substrate tied to gnd  As V in and V out become more positive  V SB increases -> V TH increases To maintain constant I D, V in -V out must increase as well Body Effect: Undesirable, complicates design of analog and digital Ics N sub and C ox has to be balanced for reasonable  device engineers’ job!!!) V TH and Body Effect

20 Noted earlier that V GD  L’  (pinch-off)  L’=f(V DS )  channel length modulation  We can then write:   Assume 1 st order relationship btwn  L/L and V DS, and define as CLM coefficient: We can re-write current equation in saturation: L L’ Channel Length Modulation

21 Channel Length Modulation (cont’d…) CLM results in non-zero slope in IV characteristics  Non-ideal current source btwn D and S in saturation regime  represents relative variation in length for a given increment in V DS Short channel -> must consider bcoz it’s bigger compared to longer channels  L/L  V DS linear approximation becomes less accurate for shorter channel  Re-write equation for current in saturation -> must rewrite equation for transconductance, g m

22 Subthreshold Conduction When V GS  V TH, weak inversion layer still exists (transistor do not fully turn off)  hence allowing some current flows from D to S  I D drops at a finite rate as V GS falls below V TH Exponential dependence on V GS  > 1 = nonideality factor, V T =kT/q Eqn similar to bipolar’s characteristic Subthreshold Conduction:  Static Power Dissipation (Leakage) a problem for large circuits (e.g. memory) Subthreshold conduction

23 MOS Layout Brief look at layout to better understand / visualize device capacitance & MOS model Layout determined by:  Electrical properties required of the device & design rules (e.g. W/L dictates g m, L governed by the process) (a) 3D view of an NMOS (b) top-view  Poly extends beyond diffusion Ensure reliable definition of edge of transistor Total S and D area minimized to minimize capacitance

24 Layout… Draw layout of circuit in (a)

25 Device Capacitances Need to consider to predict ac behavior Value of capacitance depends on bias conditions of transistor Source of capacitance:  Oxide capacitance, C depln, C overlap

26 Device cap… cont’d Oxide capacitance  Btwn gate and channel C 1 = WLC ox Depletion capacitance  Btwn channel and substrate C 2 = WL  (q  si N sub /(4  F )) Overlap capacitance  C 3 and C 4, simplest formula WL D C ox  More elaborate calculations required for accurate value Junction capacitance  Btwn S/D and substrate C bottom-plate (C j ) + C side-wall (C jsw ) C j = C jo /[1 + V R /  B ] m, V R = reverse voltage across junction,  B built-in potential, m a power in between 0.3 and 0.4

27 Layout for Low Capacitance Folded structure For layout in (a) For the same transistor in (b) Note: (b) has less C DB than (a)

28 G-S and G-D Capacitance Device off  C GD = C GS = C overlap W  C GB = C ox in series with Cdepln C ox C depln /(C ox + C depln ) Device in deep triode region (V S  V D )  C GS = C GD = C ox /2 + overlap cap = WLC ox /2 + Wc ov C ox /2 because WLCox divided equally btwn GS and GD terminals Change  V in V G draws equal amount of charge from S and D Device in saturation  C GD  Wc overlap  Non-uniform vertical electrical field in gate oxide along channel because Potential across channel varies from V S to V GS – V TH at pinch-off point  C GS = 2WL eff C ox /3 + Wc overlap C GB neglected in triode & saturation because inversion layer acts as shield btwn G and bulk. Charge supplied by S and D rather than bulk for a change in  V G

29 MOS Small Signal Models Channel length modulation modeled as  V DS Channel length modulation modeled as a resistor Body effect modeled as g m V BS

30 Models explained… Channel Length Modulation  I D varies with V DS -> modeled by a voltage- dependent current source  Note: I linearly varies with V -> linear resistor  r o affects circuit’s performance Limits amplifier gain, affect output impedance, etc.

31 Bulk Transconductance, g mb Bulk potential affects V TH hence gate-source overdrive When all other terminals held constant  I D = f(V B ) -> bulk behaves like a second gate Modeled as a dependent current-source -> g m V BS saturation  F = work function of polysilicon gate – work function of silicon substrate  F = (kT/q)[ln(N sub /n i )]

32 Gate Resistance Need to consider resistivity as well  Each terminal exhibits finite ohmic resistance  How to minimize the resistance? Folded structure? Reduces R G by 4X

33 MOS Small Signal Model with Capacitance

34 C-V of NMOS Capacitor on chip very expensive  Transistor capacitive (monolithic) NMOS: S,D, and bulk GND-ed  V G  inversion layer forms from V GS  V TH  For V G –ve Holes in substrate atrracted to oxide interface NMOS in “accummulation region” Device viewed as C ox (gate plate and substrate plate, t ox separation)  As V GS  density of interface falls Depletion region starts to form, device enters weak inversion C = C ox and C depln  For V GS > V TH Channel formed. Capacitance = C ox