Semiconductor memory utilization

Memories 2/20 Main memory map Timings Power supplying

Memories - utilization 3/20 Standard cases: Ucc A8 A9 /WE /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND SRAM 6116 (2kB) Ucc A8 A9 /WE /OE A10 /CS D7 D6 D5 D4 D3 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND EPROM 2716 (2kB) DRAM 1Mb  1 256kb  4 GND DO /CAS A9 A8 A7 A6 A5 A4 DI /WE /RAS TF A0 A1 A2 A3 Ucc GND D3 D2 /CAS /OE A8 A7 A6 A5 A4 D0 D1 /WE /RAS A0 A1 A2 A3 Ucc /WE CE2 A8 A9 A11 /OE A10 /CE1 D7 D6 D5 D4 D3 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND SRAM 8464 (8kB) Ucc /PGM A8 A9 A11 /OE A10 /CE D7 D6 D5 D4 D3 Upp A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND EPROM 2764 (8kB) Ucc /WE A13 A8 A9 A11 /OE A10 /CE D7 D6 D5 D4 D3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND PSRAM TC51832 (32kB)

Memories - utilization 4/20 timers RTC address decoders MM serv. devices interrupt controllers secondary memories processor programme memory (ROM) data memory (RAM) operator devices commu- nication devices process devices Semiconductor memories in system: main memory video memory semiconductor disks config memory data buffering memories Problems: connecting different memory chips to bus differentiating the types of memory in system

Memories - utilization 5/20 Connecting memory chips to bus ‘245 B0 B1 B2 A0 B3 : B4 A7 B5 B6 B7 /G DIR D0 D1 D2 D3 D4 D5 D6 D7 RAM /OE /WE /CE A0 : An /MREQ /RD /WR /CS ADDRADDR DATADATA Dx DI DO RAM R/W /CE A0 : An /WR /CS /RD ADDRADDR

Memories - memory map 6/20 Memory map It’s defined as assignment of different types and sizes of memories to address windows in microprocessor (microprocessor system) address space. 0000h 0800h 1000h 1800h FFFFh 4kB EPROM 2kB RAM 0000h 1000h 8000h 9000h FFFFh 4kB EPROM 4kB RAM 0000h 0800h 1000h 1800h 2000h FFFFh 2kB EPROM 2kB RAM 2kB RAM 2kB RAM 0000h 0800h 1000h 1800h 2000h FFFFh 2kB EPROM 2kB EPROM 2kB EPROM 2kB RAM

Memories - memory map 7/20 Example of memory map: precise realisation:EPROM kB: 0000h..1FFFh SRAM kB: 2000h..3FFFh not used: - 48kB: 4000h..0FFFFh

Memories - memory map 8/20 Example of memory map - simplified realisation: Effect: the same byte of memory is visible, accessible through 4 addresses, differentiating in A 15 & A 14 bits Faults: the whole memory space is used; there is no space to additional memory chips;

Memories - timings 9/20 reading ADR CE R/W D0..D7 t RC t ACE t HAD t AA t ARW t HDA t HDC Timings during reading from the memory: read cycle time - time between the begin of read cycle and the begin of the next cycle (read or write) t RC = t AA + t HAD address hold time after data valid begin data hold time after /CE signal end data hold time after address change t Ax - data valid time after the change of chosen control signal, when other signals are stable: t AA - address to data valid; t ACE - /CE low to data valid; t ARW - after the change of R/W; t A - access time - the greatest time from t Ax

Memories - timings 10/20 writing ADR CE R/W D0..D7 t WC t WR tWtW t HDW Timings during writing to the memory: address hold time after write pulse end - time between the write pulse end and the begin of next access to memory minimal write pulse time write cycle time - time between the begin of write cycle and the begin of the next cycle (read or write) data hold time after write end

Memories - timings 11/20 DATA ADDRESSES CONTROL SIGN. t B2 t B4 CPU module  P t R t RAD RAM module local decoder t D1 memory block t AA t ACS t ARW /CS t B1 t B3 Example of signals flow during memory reading:

Memories - timings 12/20 tAtA ADR  P ADR MAG CS RD  P RD MAG D PAM D MAG D  P t RAD t B3 t B4 t AA t ACS t ARW tRtR t B2 t D1 t B1 Example of time dependencies during memory reading:

Memories - timings 13/20 Correct reading conditions: C1: t RAD  t A1 = t B1 + t AA + t B3 + t B4 C2: t RAD  t A2 = t B1 + t D1 + t ACS + t B3 + t B4 C3: t RAD  t A3 = t R + t B2 + t ARW + t B3 + t B4 Example of timing analysis: Ass.: EPROM with: t AA = 200ns, t ACS = 200ns, t AOE = 75ns (t ARW )  P Z80 with clock  = 2.5MHz  t R = 150ns, t RAD = 800ns t B1, t B2, t B3, t B4 = 10ns, t D1 = 20ns C1: t A1 = t A1 = t B1 + t AA + t B3 + t B4 = = 230ns C2: t A2 = t A2 = t B1 + t D1 + t ACS + t B3 + t B4 = = 250ns C3: t A3 = t A3 = t R + t B2 + t ARW + t B3 + t B4 = = 255ns ( t A1, t A2, t A3 )  t A = 255ns < t RAD Even at  = 6MHz the given EPROM should be read correctly.

Memories - timings 14/20 DATA ADDRESSES CONTROL SIGN. t B2 t B4 CPU module  P t R t RAD RAM module local decoder t D1 memory block /CS t B1 t B3 Example of signals flow during memory writing: MRQ WR

Memories - timings 15/20 Example of time dependencies during memory writing: t B1 +t B3 t DuP1 t B3 t B1 t WuP t B2 t D1 t B1 t DuP2 t WPuP ADR  P ADR MAG CS WR  P WR MAG D  P D MAG D PAM t DHW * t WP * t DBW * t CSBW * t WR * t ABW *

Memories - timings 16/20 In the case of RAM writing cycle following should be checked:  write pulse duration generated by  P;  resultant (in designed system) times: address to write pulse begin, data to write pulse begin, chip enable to write pulse begin in comparison with memory chip datasheets;  data hold time after write pulse. Correct writing conditions : C1: t WPuP > t WP * C2: t WuP + t B2 + t WPuP - t B1 > t ABW * C3: t WuP + t B2 + t WPuP - t B1 - t D1 > t CSBW * C4: t WuP + t B2 + t WPuP - t DuP1 - t B1 - t B3 > t DBW * C5: t DuP2 + t B1 + t B3 - t WuP - t B2 - t WPuP > t DHW *

Memories - supplying 17/20 During work memory chip can use 3 values of supply current: operating current I CC - during access to chip (reading or writing); stand-by current I SB - without access to chip supplied defined operating voltage U CC ; data retention current I DR - supplies memory chip at decreasing voltage to data retention voltage U DR.

Memories - supplying 18/20 Currents I CC (operating current) & I SB (stand-by current): U CC I CC I SB CE opera- ting I SUP tt II  Q=  t  I CE opera- ting I SUP „far” charge source - supplier „near” charge source - capacitor

Memories - supplying 19/20 The supply of memory chips should be blocked near theirs supply pins by non-inductive capacitors to achieve: reducing current peaks on supply lines; increasing operation speed. Data retention in CMOS-SRAM in power-down mode: U DD VDRVDR V DR » 2V U CE > V DR -0,2V U CE 0V I SB I DR

Memories - supplying 20/20 Example of supply controlling and switching IC: