COSC 3330/6308 Solutions to First Problem Set Jehan-François Pâris September 2012

First problem (I) A program consists of two parts, namely – One part is purely sequential and takes 64 s to complete – Another part takes 1,024 s when run on a uniprocessor architecture Can be easily decomposed into two or more parallel tasks Speedup would be proportional to the number of tasks executing in parallel.

First problem (II) What would be the speedups that the program would achieve if it was to run on computers with 2, 4, 8, 16, and 32 processors? What would be the maximum speedup that the program would achieve if it was to run on a computer with an unlimited number of processors?

Answer (I) Will use Amdahl's law

Answer (II) Sequential Part (s) Number of Proc. Other Part (s) Total (s) Speedup 6411,0241,088NA infinity

Second problem Simplify the two following logical expressions: – ABC'D' + AB'D' + ACD + CD – (A  BC) (B + A) using both algebra and Karnaugh maps.

First expression (I) ABC'D' + AB'D' + ACD + CD = ABC'D' + AB'D' + CD = ABC'D' + AB'D' + AB'C'D' + CD = AC'D' + AB'D' + CD

First expression (II) C'D'C'DCDCD' A’B’0010 A’B0010 AB1010 AB’1011 AC'D' + AB'D' +CD

Second expression (I) (A  BC) (B + A) = (A(BC)' + A'BC) (A + B) = (AB' + AC' + A'BC) (A + B) = AB' + AC' + A'BC + ABC' = AB' +AC' +A'BC

Second expression (II) ABCBC A  BC A+ BPRODUCT FFFFFFF FFTFFFF FTFFFTF FTTTTTTA'BC TFFFTTTAB'C' TFTFTTTAB'C TTFFTTTABC' TTTTFTF

Second expression (III) B'C'B'CBCBC' A’0010 A1101 AB' + AC' +A'BC

Second expression (IV) A'B'A'BABAB' C’0011 C0101 AB' + AC' +A'BC

Third problem Simplify the expression – (ABC)' (A + DE)' (A  BC) (B + E) and convert it to a form that can be represented using a programmable logic array.

Answer (I) (ABC)' (A + DE)' (A  BC) (B + E) Let us do it in two parts – (ABC)' (A + DE)' = (A' + B' + C')(A'(DE)') = (A' + B' + C')(A'(D' +E') = A'(D' +E') + A'B'(D' +E') +A’C’(D’ +E’) = A'D' +A'E'

Answer (II) The second part is – (A  BC) (B + E) = (A(BC)' + A'BC)(B + E) = (AB' + AC' + A'BC)(B + E) = ABC' + A'BC + AB'E + AC'E + A'BCE

Answer (III) The product is – (A'D' +A'E')  (ABC' + A'BC + AB'E + AC'E + A'BCE) = A'BCD' + A'BCE' + A'BCD'E = A'BCD' + A'BCE' Sum of products can be represented by a PLA I checked the answer on a spreadsheet with 2 5 rows and 14 columns

Fourth problem Implement the double implication operation: – A  B = AB +A’B’ using only NAND gates.

NAND gates A nand B = (AB)' = A' + B' nand (A) nand nand(B) = (A'B')' = A + B nand(A nand B) = (AB)'' = AB nand(nand(A) nand nand(B)) = (A' B')'' = A'B'

Answer A B A'+B' A B A+B ((A + B)(A' + B')' = (A + B)' + (A' + B')' = A'B' +AB I started with a solution having more NANDs and simplified it

Fifth problem Build a regular D flip-flop using an R’S’ latch, that is, an RS latch with inverted values for R and S, and as few NOR gates as possible.

NOR gates A nor B = (A + B)' = A' B' nor (A) nor nor(B) = (A' + B')' = AB nor(A nor B) = (A+B)'' = A + B nor(nor(A) nor nor(B)) = (A' + B')'' = A' + B'

From S'R' latch to D flip-flop S'R' has three inputs – S' sets latch when S' = 0 and clock = 1 – R' resets latch when R' = 0 and clock = 1 D flip-flop – Stores a 1 at clock transition when input is 1 – Stores a 0 at clock transition when input is 0 S' R' Q' Q Clock

D flip-flop using an S-R latch X Clock S R Q Q' Clock

D flip-flop using an S'-R' latch X Clock S' R' Q Q' Clock

Introducing NORs X Clock S' R' Q Q' Clock (Clock+Clock')'=ClockClock'

Note The solution is fairly simple because we assumed that the R'S' latch had a clock entry Solution for R'S' latch without clock input is more complex Q Q’ R’ S’

Sixth problem (I) Build a synchronous sequential circuit with – Two inputs, respectively named P—for plus—and M—for minus – Two outputs respectively named O—for overflow—and U—for underflow

Sixth problem (II) The transitions are:

Answer Eight states – Three flip-flops X Y Z Will consider separately – How P inputs affect X, Y, Z – How M inputs affect X, Y, Z – When counters outputs O and U

How P inputs affect Z Y'Z'Y'ZYZYZ' P'X'0110 P'X0110 PX1001 PX’1001

Solution Z = P'Z + PZ' – Will use a T flip-flop triggered by P

How P inputs affect Y Y'Z'Y'ZYZYZ' P'X'0011 P'X0011 PX0101 PX’0101

Solution Y = P'Y + PYZ' + PY'Z – Will use a T flip-flop triggered by PZ

How P inputs affect X Y'Z'Y'ZYZYZ' P'X'0000 P'X1111 PX1101 PX’0010

Solution X = P'X + PXY' + PXZ' + PX'YZ – Will use a T flip-flop triggered by PYZ

How M inputs affect Z Y'Z'Y'ZYZYZ' M'X'0110 M'X0110 MX1001 MX’1001

Solution Z = M'Z + MZ' – Will use a T flip-flop triggered by M

How M inputs affect Y Y'Z'Y'ZYZYZ' M'X'0011 M'X0011 MX1010 MX’1010

Solution Y = M'Y + MYZ + M Y'Z' – Will use a T flip-flop triggered by MZ'

How M inputs affect X Y'Z'Y'ZYZYZ' M'X'0000 M'X1111 MX0111 MX’1000

Solution X = M'X + MXY + MXZ +MX'Y'Z' – Will use a T flip-flop triggered by MY'Z'

How P inputs affect O Y'Z'Y'ZYZYZ' P'X'0000 P'X0000 PX0010 PX’1000

Solution O = PXYZ

How M inputs affect U Y'Z'Y'ZYZYZ' M'X'0000 M'X0000 MX0000 MX’1000

Solution U = MX'Y'Z' – Will use a T flip-flop triggered by MY'Z'

Summary Flip-flops – Z: T flip-flop triggered by P + M – Y: T flip-flop triggered by PZ + MZ' – X: T flip-flop triggered by PYZ + MY'Z' Outputs – O = PXYZ – U = MX'Y'Z'