Digital Logic Design

Example 1 Find a function to detect an error in the representation of a decimal digit in BCD. In other words, write an equation with value 1 when the inputs are any one of the six unused bit combinations in the BCD code, and value 0 otherwise. Based on your equation, implement it with only NAND gates.

solution E = AB + AC.

Implementation NAND

Example 2 show how to build a 3- bit synchronous shift register using three positive edge-triggered D flip-flops and three 4-to-1 multiplexers. To apply a constant (e.g., 0 or 1) at any input, simply write the value of the constant at the input. The shift register has two control inputs Sh1 and Sh0, three data inputs D2, D1, and D0, and three data outputs Q2, Q1, and Q0. Sh1and Sh0 specify the operations of the shift register as shown in the table below. With the rotate left operation (Sh1=1, Sh0=0), all of the bits get shifted one position to the left, and Q0 gets the value of Q2. All operations must occur at the rising edge of the CLK.

Solution

Example 3 Draw the state diagram of Moore FSM that does the following: It has one serial input, X, and two serial outputs, Y and Z. Y is one if the total number of zeros received at the input since reset is odd. Z is one if the total number of zeros received at the input since reset is a multiple of three (i.e., 0, 3, 6, 9, etc.).

SOLUTION X/YZ 0/10 S0 S1 0/00 0/01 S5 S2 0/10 0/11 S4 S3 0/00

Example 4 Design a FSM circuit that is activated on a “START” signal and outputs a signal “PULSE” on a regular interval as described below. The circuit cycles through 16 clock cycle periods (0 through 15 cycles) and asserts “PULSE” on clock cycles 1, 7, 8, 15. use counter, decoder, and any extra logic

Solution state diagram Start signal =>S Pulse signal=> P We have 16 states how many binary bits will represent that? S=0/P=0 S0 S=1/P=1 S1 S=x/P=0 S2 S=x/P=0 S3 S=x/P=0 S4 S=x/P=0 S5 S=x/P=0 S11 S=x/P=0 S10 S=x/P=0 S9 S=x/P=1 S8 S=x/P=1 S7 S=x/P=1 S=x/P=0 S6 S=x/P=0 S12 S13 S15 S14 S=x/P=0 S=x/P=1 S=x/P=0

State table

Our system now 1 2 15

Example 5 Design a state diagram for a recognizer that recognizes an input sequence 11101. It has an input X and output Y. The recognizer sets the output to 1 (Y = 1) if the last five values on the input X were 11101.

state diagram 0/0 0/0 S1 S0 1/0 1/0 0/0 S5 1/0 S2 0/0 1/1 1/0 S3 S4

State table