ECE 448 – FPGA and ASIC Design with VHDL George Mason University Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL.

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Presentation transcript:

ECE 448 – FPGA and ASIC Design with VHDL George Mason University Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL

Example 1: MLU Introduction to Aldec Active-HDL

MLU Block Diagram

Experiment 1 Problem 1 ALU of PIC Microcontroller

Pertinent Components of PIC Working Register 70 W Register File (32 Registers) Address STATUS Special Function Registers General Purpose Registers

Addressing Modes Immediate mode ANDLW H’6C’ Direct mode ANDWF H’12’, 0 W & 0x6C  W W & (0x12)  W

Assembly language vs. Machine Code Assembly language mnemonic [operands] ANDLW H’6C’ Machine code ‘000101’ ‘010010’ opcode [operands] ANDWF H’12’, 0 ‘1110’ ‘ ’

Status Register STATUS 0 7 Z DC C Carry/Borrow Digit Carry (3 rd  4 th bit) Zero Power-down Time-out Program Page Preselect Reserved

Definition of the Status Register Flags (1) Z = 1 if result = 0 0 otherwise Zero flag - Z zero result C = 1 if result > MAX_UNSIGNED or result < 0 0 otherwise where MAX_UNSIGNED = for 8-bit results Carry flag - C out-of-range for unsigned numbers

Definition of the Status Register Flags (2) DC = 1 if carry from bit 3 to bit 4 (ADDWF) or no borrow from bit 4 to 3 (SUBWF) 0 otherwise Digit Carry flag – DC Carry / Borrow between MSB of first hex digit and LSB of second DC = 1

Logic Instructions 1.AND ANDWFW & RF  W or RF ANDLW W & L  W 2. Inclusive OR IORWFW | RF  W or RF IORLWW | L  W 3. Exclusive OR XORWF W  RF  W or RF XORLWW  L  W 4.Ones Complement COMF RF  RF DIR Z C DC DIR IMM DIR – DIR IMM

Arithmetic Instructions 1. Addition ADDWF W + RF  W or RF 2.Subtraction SUBWF RF – W  W or RF DIR 3.Increment INCFRF + 1  RF 4.Decrement DECFRF - 1  RF DIR Z C DC DIR –

Shifts and Rotation Instructions 1. Rotate Left Through Carry RLF 2. Rotate Right Through Carry RRF 3. Swap Nibbles SWAPFRF [7:4]  W [3:0] or RF [3:0] RF [4:0]  W [7:4] or RF [7:4] DIR Z C DC DIR – x x – – – C 0 7 C

Instruction Summary

Example 2 Mini ALU

opcode A B M R Mini ALU

MnemonicOperationOpcode ADDABR= A + B0000 ADDAMR = A + M0001 SUBABR = A - B0010 SUBAMR = A - M0011 NOTAR = NOT A0100 NOTBR = NOT B0101 NOTMR = NOT M0110 ANDABR = A AND B0111 ANDAMR = A AND M1000 ORABR = A OR B1001 ORAMR = A OR M1010 XORABR = A XOR B1011 XORAMR = A XOR M1100

Block diagram

Example 3 Variable Rotator

Function C = A <<< B A – 4-bit data input B – 2-bit rotation amount

Interface A B C

Block diagram C

Fixed Shifts in VHDL A(3)A(2) A(1) A(0) A(3)A(2)A(1) A>>1 A_shiftR <= ‘0’ & A(3 downto 1); ‘0’

Arithmetic Functions in VHDL (1) To use arithmetic operations involving std_logic_vectors you need to include the following library packages: library ieee; use ieee.std_logic_1164.all; use ieee.STD_LOGIC_UNSIGNED.ALL;

Arithmetic Functions in VHDL (2) You can use standard +, - operators to perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C<= A + B;