6-1 基本加法器 6-2 平行二進位加法器 6-3 比較器 6-4 解碼器 6-5 編碼器 6-6 數碼轉換器 6-7 多工器 ( 資料選擇器 ) 6-8 解多工器 6-9 同位元產生器 / 檢 查器

P309 半加器  A  B

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp286 half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). Half-Adder A B  C out The logic symbol and equivalent circuit are: A B  C out 

P310 全加器

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Full-Adder pp288a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. A full-adder can be constructed from two half adders as shown: A B  C out  A B   A B Sum C out C in A B  C out  C in Symbol

P bits 平行二進位加法器

P315 4 位元平行加法器

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parallel Adders Pp291 Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. AB  C out C in AB  C out C in AB  C out C in AB  C out C in A 1 B 1  C0C0    C1C1 C2C2 C3C3 C4C4 A 2 B 2 A 3 B 3 A 4 B 4 The output carry (C 4 ) is not ready until it propagates through all of the full adders. This is called ripple carry, delaying the addition process.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parallel Adders pp292The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled (C 0 ) and a Carry out (labeled C 4 ). The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the output carry delay. For the 74LS283, the maximum delay to the output carry is 17 ns. Binary number A Binary number B Input carry 4-bit sum Output carry C0C0 C4C4 

圖形式設計法 P367

P 比較器 比較器的基本功能就是比較兩個二進位數大小，以 決定兩數量的關係。最簡單形式的比較器電路可判斷兩 數是否相等。 研讀本節之後，您將具備下列能力： 利用 XOR 閘做基本比較器。 分析具有相等和不相等兩種輸出的大小比較器的內部邏 輯電路。 將 4 位元比較器擴充到可以處理 8 位元以上的信號。

相等 P319

2 Bit Magnitude Comparator

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Comparators pp300. In the simplest form, a comparator can test for equality using XNOR gates. How could you test two 4-bit numbers for equality? AND the outputs of four XNOR gates. A1B1A1B1 A2B2A2B2 A3B3A3B3 A4B4A4B4 Output

不相等 P320

4 位元大小比較器 P321

基本二進位解碼器 P323

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Comparators pp302IC comparators can be expanded using the cascading inputs as shown. The lowest order comparator has a HIGH on the A = B input. Outputs A1A1 A0A0 A2A2 A3A3 B1B1 B0B0 B2B2 B3B3 COMP A = B A < B A > B A = B A < B A > B A A A5A5 A4A4 A6A6 A7A7 B5B5 B4B4 B6B6 B7B V COMP A = B A < B A > B A = B A < B A > B A A LSBsMSBs

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Decoders pp3004A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence of the binary code 0011 are shown. The first has an active HIGH output; the second has an active LOW output. A1A1 A0A0 A2A2 A3A3 X Active HIGH decoder for 0011 A1A1 A0A0 A2A2 A3A3 X Active LOW decoder for 0011

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Decoders Assume the output of the decoder shown is a logic 1. What are the inputs to the decoder?

2-Line-to-4-Line Decoder

Figure 5.8

Truth Table for 3 to 8 Decoder Output Y1’ ~Y7’: Active LOW Input D0~D2

4 位元解碼器 P325

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Decoders pp306A specific integrated circuit decoder is the 74HC154 (shown as a 4-to-16 decoder). It includes two active LOW chip select lines which must be at the active level to enable the outputs. These lines can be used to expand the decoder to larger inputs. CS 2 A1A1 A0A0 A2A2 A3A3 CS 1 X/Y EN 74HC154

4 位元解碼器 P 某應用電路要用於檢測 5 位元數。利用 4 線對 16 線 (16 之 1) 解碼器實現此邏輯電路。二進位數以 的形式 表示。 解： 解 因為 16 之 1 解碼器只能處理 4 位元數，要檢測 5 位元就必 定要用到兩個解碼器。第 5 位元， A4 ，連接到一解碼器的晶 片選擇輸入端， 和 ， 連接到另一解碼器的致能 輸入端，如圖 6-21 所示。當十進位數在 15 以下時， ， 使低階解碼器致能，高階解碼器禁能。十進位數大於 15 時， ，故 ，使高階解碼器致能，低階解碼器禁能。

4 位元解碼器 P326 例 6-8 ( 續 ) 相關問題 當輸入二進位數 時，圖 6-21 的輸出為何？ 圖 6-21 以 16 之 1 解碼器實現的 5 位元解碼器

Seven Segment Decoder/Drivers I

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver Pp310 Another useful decoder is the 74LS47. This is a BCD-to-seven segment display with active LOW outputs. The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). BCD inputs Outputs to seven segment device GND V CC BCD/7-seg BI/RBO LT RBI LT RBI 74LS47

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver pp310 Here the 7447A is an connected to an LED seven segment display. Notice the current limiting resistors, required to prevent overdriving the LED display.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver Blanked pp311 The 74LS47 features leading zero suppression, which blanks unnecessary leading zeros but keeps significant zeros as illustrated here. The BI/RBO output is connected to the RBI input of the next decoder. Depending on the display type, current limiting resistors may be required.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver Blanked Decimal point pp311 Trailing zero suppression blanks unnecessary trailing zeros to the right of the decimal point as illustrated here. The RBI input is connected to the BI/RBO output of the following decoder.